Package substrate having main dummy pattern located in path of stress
AssigneeSamsung Electronics Co., Ltd.
InventorJong-Joo Lee
Life of this patent
Estimating the term…
Abstract
A package substrate includes an insulating substrate, a functional pattern and a main dummy pattern. A semiconductor chip is arranged on the insulating substrate. The functional pattern is formed on the insulating substrate. The functional pattern is electrically connected to the semiconductor chip. The main dummy pattern is formed on a portion of the insulating substrate at least of to the outside of and/or adjacent the functional pattern in a path of stress generated by a difference between thermal expansion coefficient of the insulating substrate and the semiconductor chip, so as to divert the stress away from the functional pattern. Thus, the stress is not concentrated on the functional pattern. As a result, damage to the functional bump caused by the stress is prevented.
Claims18
A package substrate comprising:
- an insulating substrate on which a semiconductor chip is arranged;
- a functional pattern formed on the insulating substrate, wherein the functional pattern is electrically connected to the semiconductor chip;
- and
- a main dummy pattern formed on a portion of the insulating substrate at least one of to an outside of or adjacent the functional pattern, wherein the main dummy pattern is oriented in a path of stress on the insulating substrate generated by a difference between thermal expansion coefficients of the insulating substrate and the semiconductor chip, and
- an auxiliary dummy pattern adjacent to the functional pattern, the auxiliary dummy pattern and the main dummy pattern surrounding the functional pattern.
A flip chip package comprising:
- a semiconductor chip;
- a package substrate including an insulating substrate on which the semiconductor chip is arranged, a functional pattern formed on the insulating substrate, and a main dummy pattern formed on a portion of the insulating substrate;
- a functional bump mounted on the functional pattern to electrically connect the semiconductor chip with the functional pattern;
- and
- a main dummy bump mounted on the main dummy pattern, the main dummy bump located at least one of to an outside of or adjacent the functional bump, wherein the main dummy bump is oriented in a path of stress on the insulating substrate generated by a difference between thermal expansion coefficients of the insulating substrate and the semiconductor chip, wherein the package substrate further comprises an auxiliary dummy pattern adjacent to the functional pattern, and an auxiliary dummy bump is mounted on the auxiliary dummy pattern.
A flip chip package comprising:
- a package substrate including an insulating substrate, a functional pattern formed on the insulating substrate, and a main dummy pattern formed on a portion of the insulating substrate;
- a first semiconductor chip mounted on the package substrate, the first semiconductor chip having a plug formed through the first semiconductor chip;
- a second semiconductor chip stacked on the first semiconductor chip;
- a functional bump between the plug and the functional pattern to electrically connect the first semiconductor chip with the functional pattern;
- and
- a main dummy bump mounted on the main dummy pattern, the main dummy bump located at least one of to an outside of or adjacent the functional bump, wherein the main dummy bump is oriented in a path of stress on the insulating substrate generated by a difference between thermal expansion coefficients of the insulating substrate and the first semiconductor chip.
Dependencies are inferred from the claim text.