Semiconductor package including a power plane and a ground plane

An apparatus comprising:

• a power ground/arrangement comprising
• a first semiconductor die configured as a central processing unit (CPU),
• a first metal layer, the first metal layer to provide one of (i) power signals or (ii) ground signals, and
• a second metal layer, the second metal layer to provide another one of (i) the power signals or (ii) the ground signals;
• and
• a second semiconductor die configured as a memory, the second semiconductor die being coupled to the power/ground arrangement,
• wherein the second semiconductor die is configured to receive the power signals and the ground signals from the power/ground arrangement,
• wherein the second semiconductor die is further configured to provide input signals to the first semiconductor die via the power/ground arrangement and to receive output signals from the first semiconductor die via the power/ground arrangement,
• wherein the second semiconductor die is coupled to the power/ground arrangement along a side of a periphery of the second semiconductor die,
• wherein at least one first portion of the first metal layer is exposed along an edge of the power/ground arrangement,
• wherein at least one second portion of the first semiconductor die is exposed along the edge of the power/ground arrangement, and
• wherein the second semiconductor die is coupled to the power/ground arrangement at the at least one first portion and the at least one second portion.