Complex semiconductor packages and methods of fabricating the same
AssigneeFairchild Korea Semiconductor Ltd.
InventorsGwi-gyeon Yang, Seung-won Lim
Life of this patent
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Abstract
Disclosed are complex semiconductor packages, each including a large power module package which includes a small semiconductor package, and methods of manufacturing the complex semiconductor packages. An exemplary complex semiconductor package includes a first package including: a first packaging substrate; a plurality of first semiconductor chips disposed on the first packaging substrate; and a first sealing member covering the first semiconductor chips on the first packaging substrate; and at least one second package separated from the first packaging substrate, disposed in the first sealing member, and including second semiconductor chips.
Claims22
A complex semiconductor package comprising:
- a first package having a first packaging substrate, one or more first semiconductor chips disposed on the first packaging substrate, and a first single-material layer sealing member covering the one or more first semiconductor chips and all of the first packaging substrate except for a bottom surface thereof which remains exposed from the package;
- and
- at least one second package comprising one or more second semiconductor chips and a second sealing member covering the one or more second semiconductor chips, wherein the at least one second package is separated from the first packaging substrate, disposed in the first sealing member, and completely surrounded by the first sealing member.
A complex semiconductor package comprising:
- a packaging substrate having a first surface and a second surface;
- a plurality of first semiconductor chips disposed on the first surface of the packaging substrate;
- a connecting member separately disposed from the packaging substrate;
- a plurality of first leads connected to the packaging substrate;
- a plurality of second leads connected to the connecting member;
- a first single-material layer sealing member;
- and
- at least one package disposed on the connecting member, the at least one package comprising third and fourth leads, one or more second semiconductor chips, and a second sealing member covering the one or more second semiconductor chips;
- and
- wherein the first sealing member covers the first surface and sides of the packaging substrate, the connecting member, the at least one package, and a portion of each of the first and second leads, but does not cover at least a portion of the second surface of the packaging substrate which remains exposed from the package, and wherein the first sealing member completely surrounds the at least one package.
Dependencies are inferred from the claim text.