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US 8,796,818 B2Granted
N well implants to separate blocks in a flash memory device
AssigneeMicron Technology, Inc.
InventorFrankie F. Roohparvar
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device that has an isolated area formed from one conductivity and formed in part by a buried layer of a second conductivity that is implanted in a substrate. The walls of the isolated area are formed by implants that are formed from the second conductivity and extend down to the buried layer. The isolated region has implanted source lines and is further subdivided by overlay strips of the second conductivity that extend substantially down to the buried layer. Each isolation region can contain one or more blocks of memory cells.
Claims23
A semiconductor device, comprising:
- a substrate;
- wherein the substrate includes an isolated area of a first conductivity type divided into a plurality of isolated regions of the first conductivity type by a plurality of implanted regions of a second conductivity type;
- and
- wherein a separate block of memory cells is formed in each of the plurality of isolated regions of the first conductivity type;
- and
- wherein the plurality of implanted regions of the second conductivity type comprise a plurality of regions having a first conductivity level superimposed over a plurality of areas having a second conductivity level different than the first conductivity level.
3 more elements
A semiconductor device, comprising:
- a substrate;
- wherein the substrate includes an isolated area of a first conductivity type divided into a plurality of isolated regions of the first conductivity type by a plurality of implanted regions of a second conductivity type;
- and
- wherein a separate block of memory cells is formed in each of the plurality of isolated regions of the first conductivity type;
- and
- further comprising a plurality of source lines formed in the isolated area;
- wherein the plurality of source lines are implanted into the isolated area;
- wherein the plurality of source lines comprise a plurality of n+ areas;
- and
- wherein the plurality of implanted regions of the second conductivity type comprise a plurality of n− regions superimposed over the plurality of n+ areas.
7 more elements
A semiconductor device, comprising:
- a substrate;
- wherein the substrate includes an isolated area of a first conductivity type divided into a plurality of isolated regions of the first conductivity type by a plurality of implanted regions of a second conductivity type;
- and
- wherein a separate block of memory cells is formed in each of the plurality of isolated regions of the first conductivity type;
- and
- further comprising a plurality of source lines formed in the isolated area;
- wherein the plurality of implanted regions of the second conductivity type comprise isolating strips that extend through the source lines.
4 more elements
A semiconductor device, comprising:
- a substrate;
- wherein the substrate includes an isolated area of a first conductivity type divided into a plurality of isolated regions of the first conductivity type by a plurality of implanted regions of a second conductivity type;
- wherein a separate block of memory cells is in each of the plurality of isolated regions of the first conductivity type;
- and
- further comprising a buried layer of the second conductivity type below a surface of the substrate and coupled to each of the plurality of implanted regions of the second conductivity type;
- wherein the plurality of implanted regions of the second conductivity type comprise a plurality of regions having a first conductivity level superimposed over a plurality of areas having a second conductivity level different than the first conductivity level.
3 more elements
A semiconductor device, comprising:
- a substrate;
- and
- a buried layer below a surface of the substrate;
- wherein the substrate includes an isolated area of a first conductivity type between a pair of wells of a second conductivity type that extend substantially to the buried layer;
- wherein the isolated area of the first conductivity type is divided into a plurality of isolated regions of the first conductivity type by a plurality of implanted regions of the second conductivity type, the plurality of implanted regions of the second conductivity type being coupled to the buried layer;
- wherein a plurality of source lines is implanted into the isolated area of the first conductivity type and wherein an implanted region of the second conductivity type of the plurality of isolated regions of the second conductivity type is superimposed over each source line;
- and
- wherein a separate block of memory cells is formed in each of the plurality of isolated regions of the first conductivity type.
5 more elements
Dependencies are inferred from the claim text.