US 8,796,811 B2Granted

Hybrid substrateless device with enhanced tuning efficiency

AssigneeOracle International Corporation

InventorsIvan Shubin, Ashok V. Krishnamoorthy, John E. Cunningham

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Abstract

In a hybrid integrated module, a semiconductor die is mechanically coupled face-to-face to an integrated device in which the substrate has been removed. For example, the integrated circuit may include an optical device fabricated on a silicon-on-insulator (SOI) wafer in which the backside silicon handler has been completely removed, thereby facilitating improved device performance and highly efficient thermal tuning of the operating wavelength of the optical device. Moreover, the semiconductor die may be a VLSI chip that provides power, and serves as a mechanical handler and/or an electrical driver. The thermal tuning efficiency of the substrateless optical device may be enhanced by over 100× relative to an optical device with an intact substrate, and by 5× relative to an optical device in which the substrate has only been removed in proximity to the optical device.

Claims16

Dependent claims

A hybrid integrated module, comprising:

a semiconductor die having a top surface;
an adhesive mechanically coupled to the top surface of the semiconductor die;
a first integrated device manufactured using silicon-on-insulator (SOI) technology, wherein SOI technology comprises interposing a first silicon oxide layer between a first semiconductor layer and a first silicon-handler substrate, and wherein the first semiconductor layer includes:
a top surface, wherein the top surface of the first semiconductor layer is mechanically coupled to the adhesive;
and
a bottom surface, wherein the first silicon oxide layer is disposed on the bottom surface of the first semiconductor layer;
and
a second integrated device manufactured using SOI technology, wherein SOI technology comprises interposing a second silicon oxide layer between a second semiconductor layer and a second silicon-handler substrate, and wherein the second semiconductor layer includes:
a top surface, wherein the top surface of the second semiconductor layer faces a surface of the first silicon oxide layer, thereby enabling 3-dimensional integration of the first and second integrated devices;
and
a bottom surface, wherein the second silicon oxide layer is disposed on the bottom surface of the second semiconductor layer.

8 more elements

A multi-chip module (MCM), comprising:

a first hybrid integrated module comprising:
a first semiconductor die having a top surface;
a first adhesive mechanically coupled to the top surface of the first semiconductor die;
and
a first integrated device manufactured using silicon-on-insulator (SOI) technology, wherein SOI technology comprises interposing a first silicon oxide layer between a first semiconductor layer and a first silicon-handler substrate, wherein the first semiconductor layer includes:
a top surface, wherein the top surface of the first semiconductor layer is mechanically coupled to the first adhesive;
and
a bottom surface, wherein the first silicon oxide layer is disposed on the bottom surface of the first semiconductor layer, wherein the first silicon oxide layer has a back surface on an opposite side of the first semiconductor layer;
and
a second hybrid integrated module comprising:
a second semiconductor die having a top surface;
a second adhesive mechanically coupled to the top surface of the second semiconductor die;
and
a second integrated device manufactured using SOI technology, wherein SOI technology comprises interposing a second silicon oxide layer between a second semiconductor layer and a second silicon-handler substrate, wherein the second semiconductor layer includes:
a top surface, wherein the top surface of the second semiconductor layer is mechanically coupled to the second adhesive;
and
a bottom surface, wherein the second silicon oxide layer is disposed on the bottom surface of the second semiconductor layer, wherein the second silicon oxide layer has a back surface on an opposite side of the second semiconductor layer;
and
wherein the back surfaces of the first and second silicon oxide layers face each other in the MCM.

16 more elements

Dependencies are inferred from the claim text.