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US 8,796,785 B2Granted
Semiconductor device including switch electrically connected to signal line
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorHideaki Shishido
Life of this patent
Estimating the term…
Abstract
To suppress variation of a signal in a semiconductor device. By suppressing the variation, formation of a stripe pattern in displaying an image on a semiconductor device can be suppressed, for example. A distance between two adjacent signal lines which go into a floating state in different periods (G1) is longer than a distance between two adjacent signal lines which go into a floating state in the same period (G0, G2). Consequently, variation in potential of a signal line due to capacitive coupling can be suppressed. For example, in the case where the signal line is a source signal line in an active matrix display device, formation of a stripe pattern in a displayed image can be suppressed.
Claims27
A semiconductor device comprising:
- first to n-th switches (n is a natural number of 2 or more) configured to be turned on in a first period and turned off in a second period;
- (n+1)-th to m-th switches (m is a natural number of n+2 or more) configured to be turned off in the first period and turned on in the second period;
- first to n-th signal lines;
- and
- (n+1)-th to m-th signal lines,
- wherein a signal is supplied to the first signal line in the first period through the first switch, and the first signal line is in a floating state in the second period,
- wherein a signal is supplied to the n-th signal line in the first period through the n-th switch, and the n-th signal line is in a floating state in the second period,
- wherein the (n+1)-th signal line is in a floating state in the first period, and a signal is supplied to the (n+1)-th signal tine in the second period through the (n+1)-th switch,
- wherein the m-th signal line is in a floating state in the first period, and a signal is supplied to the m-th signal line in the second period through the m-th switch,
- wherein the first to m-th signal lines are parallel or approximately parallel, wherein a distance between the n-th signal line and the (n+1)-th signal line is longer than a distance between the (n−1)-th signal line and the n-th signal line and is longer than a distance between the (n+1)-th signal line and the (n+2)-th signal line.
7 more elements
A semiconductor device comprising:
- first to n-th switches (n is a natural number of 2 or more) configured to be turned on in a first period and turned off in a second period;
- (n+1)-th to m-th switches (m is a natural number of n+2 or more) configured to be turned off in the first period and turned on in the second period;
- first to n-th source signal lines;
- and
- (n+1)-th to m-th source signal lines,
- wherein an image signal is supplied to the first source signal line in the first period through the first switch, and the first source signal line is in a floating state in the second period,
- wherein an image signal is supplied to the n-th source signal line in the first period through the n-th switch, and the n-th source signal line is in a floating state in the second period,
- wherein the (n+1)-th source signal line is in a floating state in the first period, and a signal is supplied to the (n+1)-th source signal line in the second period through the (n+1)-th switch,
- wherein the m-th source signal line is in a floating state in the first period, and a signal is supplied to the m-th source signal line in the second period through the m-th switch,
- wherein the first to m-th source signal lines are parallel or approximately parallel,
- wherein a distance between the n-th source signal line and the (n−1)-th source signal line is longer than a distance between the (n−1)-th source signal line and the n-th source signal line and is longer than a distance between the (n+1)-th source signal line and the (n+2)-th source signal line.
8 more elements
A semiconductor device comprising:
- first to n-th transistors (n is a natural number of 2 or more) configured to be turned on in a first period and turned off in a second period;
- (n+1)-th to m-th transistors (m is a natural number of n+2 or more) configured to be turned off in the first period and turned on in the second period;
- first to n-th source signal lines;
- and
- (n+1)-th to m-th source signal lines,
- wherein the first to m-th source signal lines are parallel or approximately parallel,
- wherein one of a source terminal and a drain terminal of the n-th transistor is closer to the (n+1)-th transistor than the other of the source terminal and the drain terminal of the n-th transistor,
- wherein one of a source terminal and a drain terminal of the (n+1)-th transistor is closer to the n-th transistor than the other of the source terminal and the drain terminal of the (n+1)-th transistor,
- wherein the other of the source terminal and the drain terminal of the n-th transistor is electrically connected to the n-th source signal line, and
- wherein the other of the source terminal and the drain terminal of the (n+1)-th transistor is electrically connected to the (n+1)-th source signal line.
7 more elements
Dependencies are inferred from the claim text.