Creating anisotropically diffused junctions in field effect transistor devices

A field effect transistor (FET) device, comprising:

• a silicon-on-insulator (SOI) substrate comprising a bulk substrate, a buried oxide (BOX) layer, and an SOI layer;
• a gate structure formed on the SOI layer, the gate structure comprising a gate conductor and sidewall spacers adjacent the gate conductor;
• a diffusion inhibiting species disposed in portions of the SOI layer corresponding to a channel region, self-aligned to the gate structure, the diffusion inhibiting species also disposed in portions of the BOX layer corresponding to source and drain regions;
• a first, shallow transistor dopant species implanted in the source and drain regions;
• and
• a second, deep transistor dopant species introduced in the source and drain regions;
• wherein the second transistor dopant species has a substantially vertical profile within the source and drain regions, extending to the BOX layer while the channel region is substantially free of the second transistor dopant species.