Low-noise, high-gain semiconductor device incorporating BCD (bipolar-CMOS-DMOS) technology

An semiconductor device comprising:

• a substrate having a surface;
• an n-well formed proximate to the surface of the substrate, the n-well including an n-type dopant material having a concentration of about 1×1015/cm3;
• at least two active regions formed within the n-well proximate to the surface of the substrate, the at least two active regions comprising a p-type dopant material;
• and
• a gate structure formed over the surface of the substrate between the at least two active regions, the gate structure including a doped polycrystalline layer and an oxide layer formed between the surface and the doped polycrystalline layer, the doped polycrystalline layer including the n-type dopant material having a concentration ranging from about 1×1019/cm3 to about 1×1021/cm3,
• wherein the doped polycrystalline layer further comprises a first doped polycrystalline region including the p-type dopant material having a concentration ranging from about 1×1019/cm3 to about 1×1021/cm3, a second doped polycrystalline region including the n-type dopant material having a concentration ranging from about 1×1019/cm3 to about 1×1021/cm3, and a third doped polycrystalline region including the p-type dopant material having a concentration ranging from about 1×1019/cm3 to about 1×1021/cm3, the first doped polycrystalline region and the third doped polycrystalline region comprise at least two separate and distinct regions disposed within an interior of the second doped polycrystalline region.