Buried gate transistor
AssigneeInfineon Technologies AG
InventorsRichard Lindsay, Matthias Hierlemann
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AssigneeInfineon Technologies AG
InventorsRichard Lindsay, Matthias Hierlemann
Estimating the term…
An embodiment of the invention provides a semiconductor fabrication method. The method comprises forming an isolation region between a first and a second region in a substrate, forming a recess in the substrate surface, and lining the recess with a uniform oxide. Embodiments further include doping a channel region under the bottom recess surface in the first and second regions and depositing a gate electrode material in the recess. Preferred embodiments include forming source/drain regions adjacent the channel region in the first and second regions, preferably after the step of depositing the gate electrode material. Another embodiment of the invention provides a semiconductor device comprising a recess in a surface of the first and second active regions and in the isolation region, and a dielectric layer having a uniform thickness lining the recess.
A semiconductor device having a buried gate transistor, the semiconductor device comprising:
A semiconductor device having a buried gate transistor, the semiconductor device comprising:
A semiconductor device having a buried gate transistor, the semiconductor device comprising:
Dependencies are inferred from the claim text.