US 8,796,754 B2 · Multi level programmable memory structure with multiple charge storage structures and fabricating method thereof

Abstract

A memory structure including a memory cell is provided, and the memory cell includes following elements. A first gate is disposed on a substrate. A stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure and a second charge storage structure disposed in the second dielectric structure. At least one of the first charge storage structure and the second charge storage structure includes two charge storage units which are physically separated. A first dielectric layer is disposed on the first gate at two sides of the stacked structure. A first source and drain and a second source and drain are disposed on the first dielectric layer and located at two sides of the channel layer.

Claims15

Dependent claims

A memory structure including a memory cell, the memory cell comprising:

a first gate disposed on a substrate;
a stacked structure, comprising:
a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate;
a channel output line physically connected to the channel layer;
a first charge storage structure disposed in the first dielectric structure;
and
a second charge storage structure disposed in the second dielectric structure, wherein at least one of the first charge storage structure and the second charge storage structure comprises two charge storage units which are physically separated;
a first dielectric layer disposed on the first gate at two sides of the stacked structure;
and
a first source or drain and a second source or drain disposed on the first dielectric layer and located at two sides of the channel layer.

7 more elements

A method of fabricating a memory structure, comprising:

forming a first gate on a substrate;
forming a stacked structure on the first gate, and the stacked structure comprising:
a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate;
a channel output line physically connected to the channel layer;
a first charge storage structure disposed in the first dielectric structure and including two first charge storage units which are physically separated;
and
a second charge storage structure disposed in the second dielectric structure and including two second charge storage units which are physically separated;
forming a first dielectric layer on the first gate at two sides of the stacked structure;
and
forming a first source or drain and a second source or drain on the first dielectric layer at two sides of the channel layer.

7 more elements

Dependencies are inferred from the claim text.

Multi level programmable memory structure with multiple charge storage structures and fabricating method thereof

Life of this patent

Multi level programmable memory structure with multiple charge storage structures and fabricating method thereof

Life of this patent

Abstract

Claims15