US 8,796,753 B2Granted

Nonvolatile semiconductor storage device

AssigneeKabushiki Kaisha Toshiba

InventorsTakamitsu Ishihara, Koichi Muraoka

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Abstract

According to an aspect of the present invention, there is provided a nonvolatile semiconductor storage device including: a semiconductor substrate; a source region and a drain region that are formed in the semiconductor substrate so as to be separated from each other and so as to define a channel region therebetween; a tunnel insulating film that is formed on the channel region; an insulative charge storage film that is formed on the tunnel insulating film; a conductive charge storage film that is formed on the insulative charge storage film so as to be shorter than the insulative charge storage film in a channel direction; an interlayer insulating film that is formed on the conductive charge storage film; and a gate electrode that is formed on the interlayer insulating film.

Claims8

Dependent claims

A nonvolatile semiconductor storage device, comprising:

a semiconductor substrate;
a tunnel insulating film formed on a channel region;
a charge storage layer formed on the tunnel insulating film;
an interlayer insulating film formed on the charge storage layer;
a control gate formed on the interlayer insulating film;
and
an insulating film insulating a side wall of the charge storage layer, wherein the charge storage layer comprises:
a conductive layer;
and
an insulating layer,
wherein a width of the conductive layer is smaller than a width of the insulating layer, wherein the insulating film comprises:
a portion insulating a side wall of the insulating layer;
and
a portion insulating a side wall of the conductive layer and a surface of the insulating layer at a side of the conductive layer, and
wherein the portion insulating the side wall of the insulating layer and the portion insulating the side wall of the conductive layer and the surface of the insulating layer at the side of the conductive layer comprise the same material.

12 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/146,585Filed 2 Jan 2014 · continuation
Priority: JP 2008-07210719 Mar 2008
Published: US 2014/0117433 A11 May 2014
Granted: 5 Aug 2014
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

H10D 30/687
Floating-gate IGFETs: having more than two programming levels
H10B 41/30
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the memory core region
H10D 30/681
Floating-gate IGFETs: having only two programming levels
H10D 30/6891
Floating-gate IGFETs: characterised by the shapes, relative sizes or dispositions of the floating gate electrode

Family

Application12/339,993Parent of this continuation · filed 19 Dec 2008
US 2014/0117433 A1Pre-grant publication · published 1 May 2014
US 2009/0236654 A1Published application
US 8,710,572 B2Related patent
US 8,796,753 B2This patent

From the US filing history. Foreign family members aren’t listed.