Thin film transistor array panel

A thin film transistor array panel comprising:

• a substrate comprising a display area and a peripheral area outside the display area;
• a gate line disposed in the display area of the substrate;
• a driver connection line disposed in the peripheral area of the substrate;
• a gate insulating layer disposed on the gate line and the driver connection line;
• a data line disposed on the gate insulating layer and disposed in the display area of the substrate;
• a driving pad disposed on the gate insulating layer and disposed in the peripheral area of the substrate;
• a first insulating layer disposed on the data line and the driving pad;
• a first field generating electrode disposed on the first insulating layer and disposed in the display area of the substrate;
• a connecting member disposed on the first insulating layer and disposed in the peripheral area of the substrate;
• a second insulating layer disposed on the first field generating electrode and the connecting member;
• a second field generating electrode disposed on the second insulating layer and disposed in the display area of the substrate;
• and
• a dummy electrode layer disposed on the second insulating layer and disposed in the peripheral area of the substrate,
• wherein the gate line and the driver connection line are formed with the same layer material,
• the data line and the driving pad are formed with the same layer material,
• the first field generating electrode and the connecting member are formed with the same layer material, and
• the second field generating electrode and the dummy electrode layer are formed with the same layer material.