Fan out build up substrate stackable package and method

A fan out build up substrate stackable package comprising:

• an electronic component comprising an active surface comprising a bond pad;
• a dielectric film comprising a first surface applied to the active surface of the electronic component including the bond pad, the dielectric film further comprising a second surface;
• a package body enclosing the electronic component and the dielectric film, the package body comprising a first surface coplanar with the second surface of the dielectric film;
• an integrally plated first circuit pattern formed within the dielectric film and the package body and electrically connected to the bond pad, the first circuit pattern comprising a via capture pad formed within the package body and a trace embedded within the dielectric film at the second surface of the dielectric film and within the package body at the first surface of the package body;
• and a via capture pad aperture extending through the package body and exposing the via capture pad;
• wherein the first circuit pattern further comprises:
• a bond pad via formed within the dielectric film and electrically connected to the bond pad, the trace electrically connecting the bond pad via to the via capture pad.

A fan out build up substrate stackable package comprising:

• a plated via capture pad;
• an electronic component comprising an active surface comprising adhesive thereon;
• a package body encapsulating and directly contacting the via capture pad and sides of the electronic component;
• a via capture pad aperture extending through the package body and aligned with the via capture pad;
• a first buildup dielectric layer comprising a first surface applied to a first surface of the package body, the via capture pad, and the adhesive;
• and a first circuit pattern formed in the first buildup dielectric layer, the first circuit pattern being electrically connected to a bond pad on the active surface of the electronic component and to the via capture pad, the first circuit pattern comprising a trace embedded in the first buildup dielectric layer at a second surface of the first buildup dielectric layer, where the embedded trace runs parallel to the second surface of the first buildup dielectric layer, further comprising:
• a stacked flip chip electronic component mounted to an inactive surface of the electronic component through via terminals of the electronic component that terminate respective conductive vias extending through the electronic component, wherein the package body further encapsulates the stacked flip chip electronic component.