Layer formation with reduced channel loss
AssigneeSTMicroelectronics S.r.l.
InventorsNicolas Loubet, Qing Liu, Prasanna Khare
Life of this patent
Estimating the term…
Abstract
Insulating layers can be formed over a semiconductor device region and etched in a manner that substantially reduces or prevents the amount of etching of the underlying channel region. A first insulating layer can be formed over a gate region and a semiconductor device region. A second insulating layer can be formed over the first insulating layer. A third insulating layer can be formed over the second insulating layer. A portion of the third insulating layer can be etched using a first etching process. A portion of the first and second insulating layers beneath the etched portion of the third insulating layer can be etched using at least a second etching process different from the first etching process.
Claims13
A method, comprising:
- forming a first insulating layer over a gate region and a semiconductor device region;
- forming a second insulating layer over the first insulating layer;
- forming a third insulating layer over the second insulating layer;
- etching a portion of the third insulating layer using a first etching process, wherein the second insulating layer protects the semiconductor device region during the first etching process;
- etching a portion of the first insulating layer beneath the etched portion of the third insulating layer using at least a second etching process, wherein the second etching process comprises a wet etching process;
- and
- after etching the portion of the first insulating layer, removing a remaining portion of the second insulating layer and a remaining portion of the third insulating layer such that one or more portions of the first insulating layer remains.
Dependencies are inferred from the claim text.