Optimization metallization for prevention of dielectric cracking under controlled collapse chip connections

A method comprising:

• fabricating a multi-layer chip having a plurality of metallization layers, in a process comprising:
• selectively forming first portions of said multi-layer chip comprising first stacks of layers completely through the thickness thereof, said first stacks of layers having a first modulus of elasticity;
• and
• selectively forming second portions of said multi-layer chip alongside said first portions, said second portions comprising second stacks of layers completely through the thickness thereof and having a second modulus of elasticity different from said first modulus of elasticity;
• forming a dielectric layer on said first portions and said second portions;
• and
• forming attachment pads in said dielectric layer
• said plurality of metallization layers comprising at least one layer comprising a metal pattern and at least one layer comprising low k dielectric material.

A multi-layer chip comprising:

• a first portion comprising a first stack of layers completely through the thickness thereof, said first stack of layers having a first modulus of elasticity;
• a second portion alongside said first portion, said second portion comprising a second stack of layers completely through the thickness thereof and having a second modulus of elasticity different from said first modulus of elasticity;
• a dielectric layer on said first portion and said second portion;
• and
• attachment pads above said first portion and said second portion in said dielectric layer.

A semiconductor product comprising:

• an integrated circuit chip substrate;
• an interconnection layer formed between said integrated circuit chip substrate and a package, said interconnection layer comprising a plurality of controlled collapse chip connections and an underfill material;
• said integrated circuit chip substrate comprising:
• a plurality of first portions comprising first stacks of layers completely through the thickness thereof, said first stacks of layers having a first modulus of elasticity;
• a plurality of second portions alongside said first portions, said second portions comprising second stacks of layers completely through the thickness thereof and having a second modulus of elasticity different from said first modulus of elasticity;
• and
• a dielectric layer on said first portions and said second portions;
• and
• a plurality of attachment pads in said dielectric layer, and a plurality of controlled collapse chip connections on said attachment pads.