Embedded SONOS based memory cells

A method comprising:

• implanting Indium in a first region of a substrate to form a channel of a non-volatile memory (NVM) transistor of a memory device;
• forming a dielectric stack on the substrate overlying the channel, the dielectric stack including a tunneling dielectric on the substrate and a charge-trapping layer on the tunneling dielectric, a multi-layer cap layer including a first cap layer comprising silicon-nitride overlying the charge-trapping layer, and a second cap layer comprising silicon-nitride overlying the first cap layer, wherein the second cap layer is oxygen rich relative to the first cap layer;
• and
• patterning the dielectric stack to form a gate stack of the NVM transistor in the first region of the substrate and to remove the dielectric stack from a second region of the substrate.

A method comprising:

• forming a dielectric stack on a substrate, the dielectric stack including a tunneling dielectric on the substrate, a charge-trapping layer on the tunneling dielectric, a multi-layer, silicon-nitride cap layer including a first cap layer overlying the charge-trapping layer, and a second cap layer overlying the first cap layer, and a sacrificial oxide on the second cap layer;
• patterning the dielectric stack to form a gate stack of a non-volatile memory (NVM) transistor of a memory device in a first region of the substrate while concurrently removing the dielectric stack from a second region of the substrate;
• and
• performing a gate oxidation (GOX) preclean to remove the sacrificial oxide and second cap layer from the gate stack of the NVM transistor while concurrently removing a pad oxide from the second region of the substrate, wherein the second cap layer is oxygen rich relative to the first cap layer to facilitate removal of the second cap layer.