Vertical super-thin body semiconductor on dielectric wall devices and methods of their fabrication

A method for fabricating transistor devices from a semiconductor wafer comprising at least the following steps:

• creating on the semiconductor wafer a pad oxide layer and an initial hard mask layer, such that the wafer will have at least three layers progressing from the bottom, a semiconductor layer, a pad oxide layer, and initial hard mask layer;
• performing shallow trench isolation in the semiconductor wafer through all layers to create a source/drain trench (SDT), and filling the etched SDT with a dielectric material;
• recessing the dielectric material in SDT such that the level is substantially similar to the top of the semiconductor layer;
• depositing a second hard mask layer over the semiconductor wafer such that the second hard mask is thicker than the recess depth;
• planarization of the semiconductor wafer by chemical-mechanical polishing stopping at the pad oxide layer;
• selective etching the pad oxide thereby creating a stepped surface height on the semiconductor wafer over the SDT, the surface step having an edge;
• creating a hard mask spacer adjacent to the surface step edge;
• selectively and anisotropically etching a gate trench in the semiconductor layer adjacent to and at the base of the spacer, thereby creating a vertical super-thin body (VSTB) semiconductor having the thickness of the spacer and supported by the adjoining dielectric material;
• filling the gate trench with dummy dielectric material;
• selectively and anisotropically etching the second hard mask layer and dielectric material in the SDT to form holes for source and drain electrodes (SD holes) in the SDT adjacent to the VSTB;
• forming raised source/drain layers being highly n+-doped or p+-doped for nMOSFET and pMOSFET accordingly and highly n+-doped or p+-doped regions in the VSTB for nMOSFET and pMOSFET accordingly, wherein the VSTB surface is accessed via the SD holes etched in the SDT;
• forming a pair of source and drain electrodes in the etched SD holes;
• planarizing the source and drain electrodes till the top of the dummy dielectric material;
• selectively recessing the dummy dielectric material in the gate trench to create a gate-to-substrate isolation layer;
• creating a gate stack including the gate dielectric stack and a metal gate stack in the etched gate trench adjacent to the VSTB opposite the source and drain trenches on top of the gate-to-substrate isolation layer;
• creating a gate electrode filling in the gate trench;
• and
• planarizing the gate stack layer till the top of the spacer hard mask followed with making source, drain and gate contacts.

A method for fabricating transistor devices in an array using two-dimensional self-alignment (2DSA) from a semiconductor wafer comprising at least the following steps:

• creating on the semiconductor wafer a pad oxide layer and an initial hard mask layer, such that the wafer will have at least three layers progressing from the bottom, a semiconductor layer, a pad oxide layer, and initial hard mask layer;
• performing shallow trench isolation in the semiconductor wafer through all layers to create a source/drain trench (SDT), and filling the etched SDT with a dielectric material;
• recessing the dielectric material in SDT such that the level is substantially similar to the top of the semiconductor layer;
• depositing a second hard mask layer over the semiconductor wafer such that the second hard mask is thicker than the recess depth;
• planarization of the semiconductor wafer by chemical-mechanical polishing stopping at the pad oxide layer;
• selectively etching the pad oxide thereby creating a stepped surface height on the semiconductor wafer over the SDT, the surface step having an edge;
• creating a hard mask spacer adjacent to the surface step edge;
• selectively and anisotropically etching a gate trench in the semiconductor layer adjacent to and at the base of the hard mask spacer, thereby creating a vertical super-thin body (VSTB) semiconductor having the thickness of the spacer and supported by the adjoining dielectric material;
• filling the gate trench with dummy dielectric material;
• replacing at least some of the second hard mask layer above the SDT with a first cap material at the same layer level as the hard mask spacer which allows selective etching;
• replacing some of the dummy dielectric material in the gate trench with a second cap material over the gate trench at substantially the same layer level as the hard mask spacer which allows selective etching by a different etchant than the first cap material;
• depositing an interlayer dielectric stack (ILD) above both the first and second cap material layer;
• etching a stripe recess across the gate trench and the SDT through the ILD layers to the cap layers, and the stripe recess extending to interconnect gate trenches of neighboring transistor devices in the array;
• establishing a pair of stripe spacers on either side of the stripe recess in the ILD layer;
• selectively and anisotropically etching the ILD layers, the first cap material, and the dielectric material in the SDT to form holes for source and drain electrodes (SD holes) in the SDT adjacent to the VSTB, wherein each hole is aligned by the cross-section of the VSTB hard mask spacer and the ILD stripe spacers;
• forming raised source/drain layers being highly n+-doped or p+-doped for nMOSFET and pMOSFET accordingly and highly n+-doped or p+-doped regions in the VSTB for nMOSFET and pMOSFET accordingly, wherein the VSTB surface is accessed via the SD holes etched in the SDT;
• forming a pair of source and drain electrodes in the etched SD holes;
• selectively and anisotropically etching through the second cap layer and into the dummy dielectric material in the gate trench while leaving some dummy dielectric material in the gate trench to create a gate-to-substrate isolation layer;
• creating a gate stack layer including the gate dielectric stack and a metal gate stack in the etched gate trench adjacent to the VTSB opposite the source and drain trenches on top of the gate-to-substrate isolation layer and in the stripe recess between the ILD stripe spacers;
• creating a gate electrode filling wherein the gate electrode filling fills the remaining space in the gate trench and additionally fills the stripe recess between the ILD layer stripe spacers thereby creating an electrical interconnect between the gate electrode and neighboring gate electrodes connected by the stripe recess;
• and
• making source, drain and gate contacts.

A method for fabricating transistor devices from a semiconductor wafer comprising at least the following steps:

• creating on the semiconductor wafer a pad oxide layer and an initial hard mask layer, such that the wafer will have at least three layers progressing from the bottom, a semiconductor layer, a pad oxide layer, and initial hard mask layer;
• selectively and anisotropically etching the hard mask layer and pad oxide layer away thereby creating a stepped surface on the semiconductor wafer;
• forming hard mask spacers using the stepped surface;
• performing shallow trench isolation on the semiconductor layer between hard mask spacers to create a source/drain trench (SDT), and filling the etched SDT with a dielectric material;
• selectively and anisotropically etching a gate trench through the hard mask layer, the pad oxide layer and the semiconductor layer, wherein the gate trench is bordered on at least one side by a hard mask spacer thereby creating a vertical super-thin body (VSTB) semiconductor having the thickness of the spacer and supported by the adjoining dielectric material in the SDT;
• filling the gate trench with a dummy dielectric material;
• selectively and anisotropically etching the dielectric material to form holes for source and drain electrodes (SD holes) in the SDT adjacent to the VSTB;
• forming raised source/drain layers being highly n+-doped or p+-doped for nMOSFET and pMOSFET accordingly and highly n+-doped or p+-doped regions in the VSTB for nMOSFET and pMOSFET accordingly, wherein the VSTB surface is accessed via the SD holes etched in the SDT;
• forming a pair of source and drain electrodes in the etched SD holes;
• planarizing the source and drain electrodes till the top of the dummy dielectric material;
• selectively recessing the dummy dielectric material in the gate trench to create a gate-to-substrate isolation layer;
• creating a gate stack including the gate dielectric stack and a metal gate stack in the etched gate trench adjacent to the VTSB opposite the source and drain trenches on top of the gate-to-substrate isolation layer;
• depositing a gate electrode filling in the gate trench;
• and
• planarizing the gate electrode filling till the top of the spacer hard mask followed with making SD and gate contacts.

A method for fabricating transistor devices from a semiconductor wafer comprising at least the following steps:

• creating on the semiconductor wafer a pad oxide layer and an initial hard mask layer, such that the wafer will have at least three layers progressing from the bottom, a semiconductor layer, a pad oxide layer, and initial hard mask layer;
• performing shallow trench isolation in the semiconductor wafer through all layers to create an upper electrode trench (UET), and filling the etched UET with a dielectric material;
• recessing the dielectric material in UET such that the level is substantially similar to the top of the semiconductor layer;
• depositing a second hard mask layer over the semiconductor wafer such that the second hard mask is thicker than the recess depth;
• planarization of the semiconductor wafer by chemical-mechanical polishing stopping at the pad oxide layer;
• selective etching the pad oxide thereby creating a stepped surface height on the semiconductor wafer over the UET, the surface step having an edge;
• creating a hard mask spacer adjacent to the surface step edge;
• selectively and anisotropically etching a gate trench in the semiconductor layer adjacent to and at the base of the hard mask spacer, thereby creating a vertical super-thin body (VSTB) semiconductor having the thickness of the hard mask spacer and supported by the adjoining dielectric material;
• forming a source or drain highly n+-doped or p+-doped region at the base of the gate trench for nMOSFET and pMOSFET accordingly;
• filling the gate trench with dummy dielectric material;
• selectively and anisotropically etching the second hard mask layer and dielectric material in the UET to form a hole for an upper electrode (electrode hole) in the UET adjacent to the VSTB;
• forming a raised source or drain layers being highly n+-doped or p+-doped region at the top of the VSTB for nMOSFET and pMOSFET accordingly, wherein the VSTB surface is accessed via the electrode hole etched in the UET, thereby creating a non-doped or low-doped vertical channel between the highly doped region at the top of the VSTB and the highly doped region at the base of the gate trench;
• forming an upper electrode in the etched electrode hole, the upper electrode to later be designated as either a source or a drain;
• planarizing the electrode till the top of the hard mask spacer and the top of gate dummy layer;
• selectively recessing the dummy dielectric material in the gate trench to create a gate-to-doped region isolation layer;
• creating a gate stack including the gate dielectric stack and a metal gate stack in the etched gate trench adjacent to the VTSB opposite the source and drain trenches on top of the gate-to-substrate isolation layer;
• creating a gate electrode filling in the gate trench;
• planarizing the gate electrode filling and the gate stack layer till the top of the hard mask spacer;
• selectively and anisotropically etching through the gate electrode, the gate stack, the isolation layer, and stopping on the highly doped region at the base of the gate trench creating a central electrode contact hole;
• creating an isolation spacer on the vertical walls of the central electrode contact hole;
• forming a conductive central electrode filling in the central electrode contact hole in electrical contact with the highly doped region at the base of the gate trench, the central electrode filling to later be designated as either a source or a drain;
• and
• creating contacts for the gate and the source and drain electrodes.