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US 8,796,073 B2Granted
Low cost die-to-wafer alignment/bond for 3d IC stacking
AssigneeQUALCOMM Incorporated
InventorsShiqun Gu, Thomas R. Toms
Life of this patent
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Abstract
The cost associated with alignment in a stacked IC device can be reduced by aligning multiple die instead of a single die during the alignment step. In one embodiment, the alignment structures are placed in the scribe line instead of within the die itself. Aligning four die instead of one eliminates the need for as many alignment indicators and thus more silicon on the wafer can be used for active areas. In addition, this method allows for yield improvement through binning of dies having the same yield configuration.
Claims13
A method of aligning die for a stacked IC device, comprising:
- orienting a first plurality of die for a first tier of the stacked IC device such that the first plurality has an axis of symmetry;
- orienting a second plurality of die for a second tier of the stacked IC device such that the second plurality has an axis of symmetry;
- and
- aligning the axis of symmetry of the first plurality to the axis of symmetry of the second plurality to enable stacking of the first and second pluralities of die during manufacturing of the stacked IC device.
1 more element
Dependencies are inferred from the claim text.