Reconfigurable digital signal filter processor
AssigneeBlackBerry Limited
InventorsNebu John Mathai, Oleksiy Kravets
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Abstract
A reconfigurable digital signal filter processing unit for use in a communication device is provided. The reconfigurable filters processor can implement different filter topologies to adapt to a range or wireless technology characteristics. The reconfigurable filter processor comprises a plurality of filter blocks whose inputs can be selected based on the desired configuration of the filter. Each filter block applies a transfer function to a received signal to achieve a desired filtering function.
Claims20
A reconfigurable digital signal filter processing unit comprising:
- an input filter block for applying an input transfer function to an input to the reconfigurable digital signal filter processing unit and generating a filter block output according to the input transfer function;
- a plurality of filter blocks each for applying a transfer function to a filter block input and generating a filter block output according to the respective transfer function;
- a combiner for selectively combining filter block outputs from at least two filter blocks of the plurality of filter blocks and generating a combiner output;
- wherein the respective filter block input of each of the plurality of filter blocks is selectively coupled to:
- a filter block output of one of the plurality of filter blocks or the filter block output of the input filter block;
- and
- the combiner output.
A reconfigurable digital signal filter processing unit for producing a filtered output from an input, the processing unit comprising:
- a. a first filter block coupled the input and providing an output (U0) according to a first transfer function;
- b. a second filter block selectably receiving one of U0 and an alternate input (Yc) and providing an output (Un) according to a second transfer function;
- c. a third filter block selectably receiving one of the input and Un and providing an output (L0) according to a third transfer function;
- d. a fourth filter block selectably receiving one of L0 and Un and providing an output (L1) according to a fourth transfer function;
- and
- e. a combiner selectably combining U0 with L0 or U1 with L1 to provide the alternate input Yc, the alternate input Yc coupled to the output.
A method of reconfiguring a digital signal filter processing unit comprising:
- receiving an input indicating an order of a lattice wave digital filter (LWDF) section and a serial cascaded filter section;
- determining a plurality of control signals required for coupling a plurality of filter blocks together to provide the filter sections specified by the input;
- and
- applying the determined control signals to respective filter block multiplexers, each filter block multiplexer associated with one of the plurality of filter blocks and for selecting an input of the filter block.
Dependencies are inferred from the claim text.