# US 8,789,169 B2 · Microcomputer having a protection function in a register > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,789,169 B2 - Document ID: US8789169B2 - Status: Granted - Kind: B2 - Application number: 12/783,252 - Filed: 2010-05-19 - Published: 2010-11-25 - Granted: 2014-07-22 - Earliest claimed: 2009-05-22 - Assignees: Renesas Electronics Corporation - Applicants: Sugako Otani; Hiroyuki Kondo - Inventors: Sugako Otani; Hiroyuki Kondo - Web page: https://patentgrep.com/patent/US8789169B2 ## CPC - G06F 9/30123: {according to context, e.g. thread buffers} - G06F 9/30054: {Unconditional branch instructions} - G06F 9/30138: {Extension of register space, e.g. register cache} - G06F 9/30189: {according to execution mode, e.g. mode flag} - G06F 9/323: {for indirect branch instructions} - G06F 9/3861: {Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A control unit controls execution of an instruction according to a decode result of an instruction code. A GRA register stores an access attribute for each of the plurality of general-purpose registers. A mode storage unit stores modes for controlling an operation of a CPU. When the control unit makes a request for access to the general-purpose register, register access allowance determining circuit determines whether the access to the general-purpose register in question is to be allowed or not, depending on the access attribute stored in the GRA register and the mode stored in the mode storage unit. Therefore, the number of the general-purpose registers used corresponding to the mode can be changed, and efficiency of use of the general-purpose registers can be optimized. ## Claims ### Claim 1 A microcomputer including a processor for executing instructions, and comprising: a control unit for controlling execution of the instruction according to results of decoding of instruction codes; a first bus; a second bus; a general-purpose register file coupled between the first bus and the second bus and including a plurality of general-purpose registers; an operation unit coupled between the first bus and the second bus and configured to receive data to be processed from the general-purpose register file and to output an operation result to the general-purpose register file; an access attribute storage unit for storing an access attribute for each of said plurality of general-purpose registers; a mode storage unit for storing a mode for controlling an operation of said processor; and an access determining unit for determining, when a request for access to a general-purpose register of the plurality of general-purpose registers is made by said control unit, whether access to the general-purpose register is to be allowed or not, depending on the access attribute stored in said access attribute storage unit and the mode stored in said mode storage unit wherein when an exception request occurs, the access attribute stored in said access attribute storage unit is saved in another storage area, and the mode stored in said mode storage unit is changed. ### Claim 2 (depends on 1) The microcomputer according to claim 1, wherein said access determining unit provides an exception request to said control unit when the access to the general-purpose register is not allowed. ### Claim 3 (depends on 1) The microcomputer according to claim 1, wherein said access determining unit allows only the access to the general-purpose register of which access allowance is set by the access attribute stored in said access attribute storage unit, when the mode stored in said mode storage unit is a first mode, and allows the access to all the general-purpose registers when the mode stored in said mode storage unit is a second mode. ### Claim 4 (depends on 1) The microcomputer according to claim 1, wherein said access determining unit allows only the access to the general-purpose register of which access allowance is set by the access attribute stored in said access attribute storage unit, when the mode stored in said mode storage unit is a first mode, and allows only the access to the general-purpose register of which access prohibition is set by the access attribute stored in said access attribute storage unit, when the mode stored in said mode storage unit is a second mode. ### Claim 5 A microcomputer including a processor for executing an instruction while accessing a plurality of general purpose registers, and comprising: a control unit for controlling execution of the instruction according to a result of decoding of an instruction code; an access attribute storage unit for storing an access attribute for each of said plurality of general purpose registers; a mode storage unit for storing a mode for controlling an operation of said processor; and an access determining unit for determining whether access to the general purpose register is to be allowed or not, depending on the access attribute stored in said access attribute storage unit and the mode stored in said mode storage unit, when a request for the access to the general purpose register is made by said control unit, wherein when an exception request occurs, the access attribute stored in said access attribute storage unit is saved in another storage area, and the mode stored in said mode storage unit is changed. ### Claim 6 (depends on 5) The microcomputer according to claim 5, wherein said access determining unit provides an exception request to said control unit when the access to the general-purpose register is not allowed. ### Claim 7 (depends on 5) The microcomputer according to claim 5, wherein said access determining unit allows only the access to the general-purpose register of which access allowance is set by the access attribute stored in said access attribute storage unit, when the mode stored in said mode storage unit is a first mode, and allows the access to all the general-purpose registers when the mode stored in said mode storage unit is a second mode. ### Claim 8 (depends on 5) The microcomputer according to claim 5, wherein said access determining unit allows only the access to the general-purpose register of which access allowance is set by the access attribute stored in said access attribute storage unit, when the mode stored in said mode storage unit is a first mode, and allows only the access to the general-purpose register of which access prohibition is set by the access attribute stored in said access attribute storage unit, when the mode stored in said mode storage unit is a second mode. ### Claim 9 (depends on 7) The microcomputer according to claim 7, wherein said first mode corresponds to a user mode, and said second mode corresponds to a supervisor mode. ### Claim 10 (depends on 7) The microcomputer according to claim 7, wherein said first mode corresponds to a mode for executing an application program, and said second mode corresponds to a mode for executing an interrupt processing routine. ### Claim 11 (depends on 7) The microcomputer according to claim 7, wherein said processor has a plurality of privilege levels, and a part of said plurality of privilege levels are allocated to said first mode, and the other privilege levels are allocated to said second mode. ### Claim 12 (depends on 5) The microcomputer according to claim 5, wherein said access attribute storage unit stores a kind of the access allowed to each of said plurality of general-purpose registers, and when said control unit makes the request for the access to the general-purpose register, said access determining unit determines whether the access to the general-purpose register is to be allowed or not, depending on the kind of the allowed access stored in said access attribute storage unit and the mode stored in said mode storage unit. ### Claim 13 (depends on 5) The microcomputer according to claim 5, wherein said plurality of general-purpose registers are divided into a plurality of groups, said access attribute storage unit stores a group selected from among said plurality of groups for allowing the access, and when said control unit makes the request for the access to the general-purpose register, said access determining unit determines whether the access to the general-purpose register is to be allowed or not, depending on the group stored, for allowing the access, in said access attribute storage unit and the mode stored in said mode storage unit. ### Claim 14 (depends on 5) The microcomputer according to claim 5, wherein said access attribute storage unit stores, for each of said plurality of general-purpose registers, a predetermined unit of data to which access is to be allowed, and when said control unit makes the request for the access to the general-purpose register, said access determining unit determines whether the access to the general-purpose register is to be allowed or not, depending on information stored in said access attribute storage unit and relating to the predetermined unit of the data for allowing the access, and the mode stored in said mode storage unit. ### Claim 15 (depends on 5) The microcomputer according to claim 5, wherein said processor has a plurality of privilege levels, said access attribute storage unit stores, for each of said plurality of general-purpose registers, the privilege level from which access is to be allowed, and when said control unit makes the request for the access to the general-purpose register, said access determining unit determines whether the access to the general-purpose register is to be allowed or not, depending on information stored in said access attribute storage unit and relating to the privilege level for allowing the access, and the mode stored in said mode storage unit. ### Claim 16 (depends on 5) The microcomputer according to claim 5, further comprising: a first decoder for decoding the instruction code by interpreting the instruction code as an instruction code corresponding to a first mode; a second decoder for decoding the instruction code by interpreting the instruction code as an instruction code corresponding to a second mode; and a selector for selectively providing a decode result of said first decoder and a decode result of said second decoder to said control unit, depending on the mode stored in said mode storage unit. ### Claim 17 (depends on 16) The microcomputer according to claim 16, wherein said first decoder performs the decoding by interpreting as an operation code a part of a portion which is included in the instruction code and is interpreted by said second decoder as a register-designation field. ### Claim 18 (depends on 5) The microcomputer according to claim 5, wherein said access attribute storage unit is mounted as a control register. ### Claim 19 (depends on 5) The microcomputer according to claim 5, wherein said access attribute storage unit is mapped in an address space. ### Claim 20 (depends on 5) The microcomputer according to claim 5, wherein said access attribute storage unit stores information received from an outside of said processor.