# US 8,789,005 B1 · Method and apparatus for efficiently processing an integrated circuit layout > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,789,005 B1 - Document ID: US8789005B1 - Status: Granted - Kind: B1 - Application number: 13/463,817 - Filed: 2012-05-04 - Granted: 2014-07-22 - Earliest claimed: 2012-05-04 - Assignees: Cadence Design Systems, Inc. - Applicants: Kimiko Umino; David C. Noice - Inventors: Kimiko Umino; David C. Noice - Web page: https://patentgrep.com/patent/US8789005B1 ## CPC - G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) - G06F 30/39: Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A method for efficiently processing a design layout is described. In some embodiments, the method receives an original design layout and a modified design layout. The method identifies a change from the original design layout to the modified design layout by comparing the original and modified design layouts. The method of some embodiments then defines a region based on the location of the identified change within the modified design layout. The method performs a design operation (e.g., placing fills) only on the identified region of the modified design layout. ## Claims ### Claim 1 A computer-implemented method for performing a design operation on a circuit design layout, the method comprising: at a computer, receiving a first design layout comprising a first set of shapes and a second design layout comprising a second set of shapes and a plurality of sections; comparing the first design layout with the second design layout to identify an area of the second design layout that differs from a corresponding area of the first design layout in that one of the areas comprises a portion of a shape that the other area does not have; identifying a set of the sections of the second design layout which include the identified area of the second design layout; and performing a design operation only on the identified set of sections of the second design layout. ### Claim 2 (depends on 1) The method of claim 1, wherein performing the design operation comprises verifying the identified region against a design rule. ### Claim 3 (depends on 1) The method of claim 1, wherein performing the design operation comprises checking density of the identified region. ### Claim 4 (depends on 1) The method of claim 1, wherein performing the design operation comprises placing metal fills in the identified region. ### Claim 5 (depends on 1) The method of claim 1, wherein the first and second design layouts are different versions of the same design layout. ### Claim 6 (depends on 1) The method of claim 1, wherein the first and second design layouts have a same dimension. ### Claim 7 (depends on 1) The method of claim 1, wherein a shape in a design layout represents at least one of a net, a via, a pin, and a fill. ### Claim 8 A non-transitory machine readable medium storing a program for performing design operations on a circuit design layout, the program comprising sets of instructions for: modifying a first set of shapes of an original circuit design layout to generate a modified circuit design layout comprising a second set of shapes and a plurality of sections; comparing the original circuit design layout with the modified circuit design layout to identify a set of sections of the modified circuit design layout, said set of sections including a portion of a shape in the modified circuit design layout that has been changed from the original circuit design layout; and performing a set of metal fill placement operations only on the identified set of sections of the modified circuit design layout. ### Claim 9 (depends on 8) The machine readable medium of claim 8, wherein the set of instructions for modifying the first set of shapes comprises a set of instructions for reshaping at least one shape in the first set of shapes in the circuit design layout. ### Claim 10 (depends on 8) The machine readable medium of claim 8, wherein the set of instructions for modifying the first set of shapes comprises a set of instructions for adding at least a portion of at least one shape to the circuit design layout. ### Claim 11 (depends on 8) The machine readable medium of claim 8, wherein the set of instructions for modifying the first set of shapes comprises a set of instructions for removing at least a portion of at least one shape in the first set of shapes from the circuit design layout. ### Claim 12 (depends on 8) The machine readable medium of claim 8, wherein the changed region of the modified circuit design layout comprises an area of the modified circuit design layout that is within a certain distance from the portion of the shape. ### Claim 13 (depends on 8) The machine readable medium of claim 8, wherein the program further comprises a set of instructions for defining a blocked region in the original circuit design layout, wherein the set of instructions for performing the set of metal fill placement operations comprises a set of instructions for excluding any portion of the identified region from the identified region when the portion overlaps with the blocked region. ### Claim 14 (depends on 13) The machine readable medium of claim 13, wherein the program further comprises a set of instructions for receiving user inputs, wherein the set of instructions for defining the blocked region comprises a set of instructions for defining the blocked region based on the user inputs. ### Claim 15 (depends on 8) The machine readable medium of claim 8, wherein the set of metal fill placement operations includes modifying the modified circuit design layout. ### Claim 16 (depends on 8) The non-transitory machine readable medium of claim 8, wherein the set of metal fill placement operations includes a density checking operation. ### Claim 17 A system comprising: a processor for executing sets of instructions; and a memory for storing a computer program for performing design operations, the program comprises sets of instructions for: storing a copy of a circuit design layout before a shape in a circuit design layout is modified; identifying sections of the modified circuit design layout that contain the modified shape by comparing the modified circuit design layout with the stored copy of the circuit design layout; and performing a set of design rule checking (DRC) operations only on set of sections of the circuit design layout that include the identified location. ### Claim 18 (depends on 17) The system of claim 17, wherein the program further comprises a set of instructions for defining a region that includes the identified location of the modified shape. ### Claim 19 (depends on 18) The system of claim 18, wherein the defined region is within a certain distance from the identified location. ### Claim 20 (depends on 18) The system of claim 18, wherein the set of instructions for defining the region comprises sets of instructions for: dividing the design layout into a set of grids; and using grids to define the region. ### Claim 21 (depends on 18) The system of claim 18, wherein the program further comprises a set of instructions for modifying another shape that is in the region based on results of performing the DRC operations.