# US 8,789,002 B2 · Method for manufacturing semiconductor device on the basis of changed design layout data

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 8,789,002 B2
- Document ID: US8789002B2
- Status: Granted
- Kind: B2
- Application number: 12/339,652
- Filed: 2008-12-19
- Published: 2009-07-02
- Granted: 2014-07-22
- Earliest claimed: 2007-12-26
- Assignees: Fujitsu Semiconductor Limited
- Applicants: Takuji Tanaka
- Inventors: Takuji Tanaka
- Web page: https://patentgrep.com/patent/US8789002B2

## CPC

- G06F 30/39: Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347)
- H10D 89/10: Integrated device layouts
- H10D 84/903: {comprising field effect technology}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of manufacturing a semiconductor device on the basis of changed design layout data. The method decides a functional relationship between layout parameters based on layout data and the electrical characteristic of a plurality of semiconductor elements. Candidates of the values of the layout parameters are extracted from design layout data so as to decrease the difference between a target electrical characteristic and a predicted electrical characteristic. A specific value from the candidate values of the layout parameters is selected and the design layout data is changed based on the specific selected value.

## Claims

### Claim 1

A method of manufacturing a semiconductor device comprising:
measuring an electrical characteristic of a plurality of semiconductor elements;
defining layout parameters on the basis of layout data of the plurality of semiconductor elements and deciding a functional relationship between the layout parameters and the electrical characteristic;
extracting values of the layout parameters from design layout data of the semiconductor device;
calculating a predicted electrical characteristic of the semiconductor device on the basis of the values of the layout parameters and the functional relationship;
calculating a difference between a target electrical characteristic and the predicted electrical characteristic of the semiconductor device;
obtaining a second mapping relationship from the electrical characteristic to the layout parameters, which is an inverse function of a first mapping relationship from the layout parameters to the electrical characteristic, based on the first mapping relationship;
generating, by using the second mapping relationship, a plurality of candidates of the values of the layout parameters which make the predicted electrical characteristic approximate to the target electrical characteristic;
selecting a specific value from among the candidates so as to decrease the difference between the target electrical characteristic and the predicted electrical characteristic;
changing the design layout data based on the specific value;
manufacturing the semiconductor device on the basis of the changed design layout data;
calculating a partial differential coefficient by differentiating the functional relationship with respect to the layout parameters; and
selecting the specific value in a range where the partial differential coefficient is equal to or larger than a predetermined reference value in a direction in which square of the difference decreases.

### Claim 2 (depends on 1)

The method according to claim 1, wherein a value which satisfies a design layout rule, is selected in selecting the specific value.

### Claim 3 (depends on 1)

The method according to claim 1, wherein different weights are given to the difference between the target electrical characteristic and the predicted electrical characteristic about a plurality of types of the electrical characteristic of the plurality of semiconductor elements in selecting the specific value.

### Claim 4 (depends on 1)

The method according to claim 1, the electrical characteristic includes any one of a threshold voltage of a transistor, an on-current, an off-leak current, delay time of a logic circuit, and a life of the element.

### Claim 5 (depends on 1)

The method according to claim 1, wherein the layout parameters include at least one of a gate length, a gate width, a pitch to an adjacent gate, a gate length of the adjacent gate, a width of an active region, a distance to an adjacent active region, and a width of the adjacent active region.

### Claim 6 (depends on 1)

The method according to claim 1, further comprising:
determining whether the design layout data after a correction satisfies a mask design rule.

### Claim 7 (depends on 1)

The method according to claim 1, further comprising:
determining whether the design layout data after a correction satisfies a rule recommended in manufacturing.

### Claim 8 (depends on 1)

The method according to claim 1, wherein the layout parameters include two or more of a gate length, a gate width, a pitch to an adjacent gate, a gate length of the adjacent gate, a width of an active region, a distance to an adjacent active region, and a width of the adjacent active region.