# US 8,788,998 B2 · Non-integer height standard cell library

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- Number: US 8,788,998 B2
- Document ID: US8788998B2
- Status: Granted
- Kind: B2
- Application number: 13/725,870
- Filed: 2012-12-21
- Published: 2014-06-26
- Granted: 2014-07-22
- Earliest claimed: 2012-12-21
- Assignees: Broadcom Corporation
- Applicants: Broadcom Corporation
- Inventors: Mehdi Hatamian; Paul Penzes
- Web page: https://patentgrep.com/patent/US8788998B2

## CPC

- G06F 30/392: Floor-planning or layout, e.g. partitioning or placement
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A standard cell library for designing integrated circuits is provided. In some aspects, the standard cell library includes a plurality of standard cells having a cell height that is a non-integer multiple of a wiring pitch of routing tracks associated with the standard cell library. The standard cell library further includes a plurality of landing pins for connecting to the routing tracks arranged in the plurality of standard cells, wherein each of the plurality of landing pins is extended by half of the wiring pitch in opposite directions orthogonal to an orientation of the routing tracks.

## Claims

### Claim 1

An integrated circuit designed using a standard cell library, comprising:
a plurality of standard cells having a cell height that is a non-integer multiple of a wiring pitch of routing tracks associated with the plurality of standard cells, wherein the plurality of standard cells are arranged in a plurality of adjacent rows, and wherein standard cells associated with each row of the plurality of adjacent rows have an orientation that is opposite of an orientation of standard cells associated with adjacent rows of the plurality of adjacent rows, and
a plurality of landing pins for connecting to the routing tracks arranged in the plurality of standard cells, wherein each of the plurality of landing pins is extended by half of the wiring pitch in opposite directions orthogonal to an orientation of the routing tracks.

### Claim 2 (depends on 1)

The integrated circuit of claim 1, wherein the plurality of standard cells comprises one or more fin-based field effect transistors, and wherein the cell height of the plurality of standard cells is an integer multiple of a height of the fin-based field effect transistors.

### Claim 3 (depends on 2)

The integrated circuit of claim 2, wherein a fin pitch of the one or more fin-based field effect transistors is not a divisor of the wiring pitch of the routing tracks associated with the standard cell library.

### Claim 4 (depends on 1)

The integrated circuit of claim 1, further comprising one or more sets of landing pins collinearly aligned to form one or more columns of landing pins orthogonal to the orientation of the routing tracks.

### Claim 5

A computer program product comprising instructions stored in a tangible computer-readable storage medium, the instructions comprising:
instructions for arranging a plurality of standard cells in rows, the plurality of standard cells having a cell height that is a non-integer multiple of a wiring pitch of routing tracks associated with the standard cell library;
instructions for arranging a plurality of landing pins within the plurality of standard cells to collinearly align to form one or more columns of landing pins orthogonal to an orientation of the routing tracks; and
instructions for extending two or more landing pins associated with each of the one or more columns of landing pins by half of the wiring pitch in opposite directions orthogonal to the orientation of the routing tracks.

### Claim 6 (depends on 5)

The computer program product of claim 5, wherein landing pins located at each end of the one or more columns of landing pins are extended by half of the wiring pitch.

### Claim 7 (depends on 5)

The computer program product of claim 5, wherein the plurality of standard cells comprises one or more fin-based field effect transistors, and
wherein the cell height of the plurality of standard cells is an integer multiple of a height of the fin-based field effect transistors.

### Claim 8 (depends on 7)

The computer program product of claim 7, wherein a fin pitch of the one or more fin-based field effect transistors is not a divisor of the wiring pitch of the routing tracks associated with the standard cell library.

### Claim 9 (depends on 5)

The computer program product of claim 5, further comprising:
arranging the plurality of standard cells into a plurality of adjacent rows, wherein
standard cells associated with each row of the plurality of adjacent rows have an orientation that is opposite of an orientation of standard cells associated with adjacent rows of the plurality of layers.

### Claim 10

An integrated circuit using standard cells of a standard cell library, the integrated circuit comprising:
a plurality of standard cells having a cell height that is a non-integer multiple of a wiring pitch of routing tracks associated with the standard cell library; and
a plurality of landing pins for connecting to the routing tracks arranged in the plurality of standard cells, wherein each of the plurality of landing pins is extended by half of the wiring pitch in opposite directions orthogonal to an orientation of the routing tracks.

### Claim 11 (depends on 10)

The integrated circuit of claim 10, wherein the plurality of standard cells comprises one or more fin-based field effect transistors, and
wherein the cell height of the plurality of standard cells is an integer multiple of a height of the fin-based field effect transistors.

### Claim 12 (depends on 11)

The integrated circuit of claim 11, wherein a fin pitch of the one or more fin-based field effect transistors is not a divisor of the wiring pitch of the routing tracks associated with the standard cell library.

### Claim 13 (depends on 10)

The integrated circuit of claim 10, further comprising one or more sets of landing pins collinearly aligned to form one or more columns of landing pins orthogonal to the orientation of the routing tracks.