# US 8,788,987 B2 · Rescaling

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- Number: US 8,788,987 B2
- Document ID: US8788987B2
- Status: Granted
- Kind: B2
- Application number: 13/806,767
- Filed: 2011-04-06
- Published: 2013-04-18
- Granted: 2014-07-22
- Earliest claimed: 2010-06-23
- Assignees: Tabula, Inc.
- Applicants: Scott J. Weber; Christopher D. Ebeling; Andrew Caldwell; Steven Teig; Timothy J. Callahan; Hung Q. Nguyen; Shangzhi Sun; Shilpa V. Yeole
- Inventors: Scott J. Weber; Christopher D. Ebeling; Andrew Caldwell; Steven Teig; Timothy J. Callahan; Hung Q. Nguyen; Shangzhi Sun; Shilpa V. Yeole
- Web page: https://patentgrep.com/patent/US8788987B2

## CPC

- G06F 30/394: Routing (G06F30/396 takes precedence)
- G06F 30/30: Circuit design
- G06F 30/327: Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
- G06F 30/34: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
- G06F 30/347: Physical level, e.g. placement or routing
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A novel method for designing an integrated circuit (“IC”) by rescaling an original set of circuits in a design of the IC is disclosed. The original set of circuits to be rescaled includes sequential nodes, combinational nodes, and interconnects. Each sequential node is associated with a phase of a clock. The method generates a rescaled set of circuits that includes multiple replica sets of the circuits. Each replica set of circuits includes sequential nodes, combinational nodes, and interconnects that are identical to nodes and interconnects in the original set of circuits. Each sequential node is associated with a phase of a clock that is at a fraction of the phase of its corresponding sequential element in the original set. The method connects nodes in each replica set of circuits to a logically equivalent node in another replica set. The method replaces the original set of circuits with the rescaled set of circuits.

## Claims

### Claim 1

An integrated circuit (IC) comprising:
a set of configurable circuits for performing a user design that is defined to operate based on a user design cycle, the set of configurable circuits comprising a plurality of sets of sequential elements, wherein different sets of sequential elements operate at different phases of the user design cycle, each set of sequential elements that operates at a particular phase of the user design cycle receiving inputs from another set of the plurality of sets of sequential elements operating in another phase of the user design cycle; and
a routing circuit for switchably receiving outputs from each of the plurality of sets of sequential elements, wherein the routing circuit produces an output from a different set of sequential elements in each phase of the user design cycle.

### Claim 2 (depends on 1)

The IC of claim 1, wherein a first sequential element operating at a first phase of the user design cycle receives input from a second sequential element operating at a second, different phase of the user design cycle via at least one intervening combinational element.

### Claim 3 (depends on 2)

The IC of claim 2, wherein the second phase is an earlier phase in the user design cycle than the first phase.

### Claim 4 (depends on 2)

The IC of claim 2, wherein the first phase is the earliest phase in the user design cycle and the second phase is a latest phase in the user design cycle.

### Claim 5 (depends on 2)

The IC of claim 2, wherein the intervening combinational element is a reconfigurable logic circuit.

### Claim 6 (depends on 1)

The IC of claim 1, wherein the set of configurable circuits are reconfigurable circuits that reconfigure every reconfiguration cycle, wherein each user design cycle comprises a plurality of reconfiguration cycles.

### Claim 7

An integrated circuit (IC) comprising:
a plurality of reconfigurable circuits for performing a user design that is defined based on a user design cycle, the plurality of reconfigurable circuits comprising a set of storage elements, wherein different subsets of the set of storage elements stores data in different sub-cycles of the user design cycle, each subset storing data received from another subset of the set of storage elements; and
a plurality of configuration data storage that stores a plurality of configuration data sets for reconfiguring the plurality of reconfigurable circuits a plurality of times during each user design cycle.

### Claim 8 (depends on 7)

The IC of claim 7, wherein each of the subsets of the set of storage elements stores data in only one sub-cycle of the user design cycle.

### Claim 9 (depends on 7)

The IC of claim 7, wherein each storage element operating in a particular sub-cycle receives data that originates from storage elements operating in another sub-cycle without any intervening storage element from a storage elements that operates in the particular sub-cycle.

### Claim 10 (depends on 7)

The IC of claim 7, wherein a first storage element operating in a first sub-cycle receives an input data from a second storage element operating in a second, different sub-cycle without any intervening storage element that operate in the first sub-cycle.

### Claim 11 (depends on 10)

The IC of claim 10, wherein the first storage element receives said input data from the second storage element via an intervening combinational element.

### Claim 12 (depends on 11)

The IC of claim 11, wherein the intervening combinational element is a look-up table (LUT).

### Claim 13 (depends on 11)

The IC of claim 11, wherein the intervening combinational element reconfigures a plurality of times during each user design cycle.

### Claim 14 (depends on 7)

The IC of claim 7, wherein each sub-cycle corresponds to a phase of the user design cycle.

### Claim 15

An electronic device comprising:
an integrated circuit (IC) comprising:
a set of configurable circuits for performing a user design that is defined to operate based on a user design cycle, the set of configurable circuits comprising a plurality of sets of sequential elements, wherein different sets of sequential elements are for operating at different phases of the user design cycle, each set of sequential elements that operates at a particular phase of the user design cycle receiving inputs from another set of the plurality of sets of sequential elements operating at another phase of the user design cycle; and
a routing circuit for switchably providing inputs to each of the plurality of sets of sequential elements, wherein the routing circuit produces the inputs for a different set of sequential elements in each phase of the user design cycle; and
a memory device for providing data to the IC.

### Claim 16 (depends on 15)

The electronic device of claim 15, wherein a first sequential element operating at a first phase of the user design cycle receives input from a second sequential element operating at a second, different phase of the user design cycle via at least one intervening combinational element.

### Claim 17 (depends on 16)

The electronic device of claim 16, wherein the second phase is an earlier phase in the user design cycle than the first phase.

### Claim 18 (depends on 16)

The electronic device of claim 16, wherein the first phase is an earliest phase in the user design cycle and the second phase is a latest phase in the user design cycle.

### Claim 19 (depends on 16)

The electronic device of claim 16, wherein the intervening combinational element is a reconfigurable logic circuit.

### Claim 20 (depends on 15)

The electronic device of claim 15, wherein the set of configurable circuits are reconfigurable circuits that reconfigure every reconfiguration cycle, wherein each user design cycle comprises a plurality of reconfiguration cycles.