# US 8,788,986 B2 · System and method for capacity planning for systems with multithreaded multicore multiprocessor resources

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- Number: US 8,788,986 B2
- Document ID: US8788986B2
- Status: Granted
- Kind: B2
- Application number: 12/927,761
- Filed: 2010-11-22
- Published: 2012-05-24
- Granted: 2014-07-22
- Earliest claimed: 2010-11-22
- Assignees: CA, Inc.
- Applicants: Kenneth C. Zink; Douglas M. Neuse; Christopher B. Walton
- Inventors: Kenneth C. Zink; Douglas M. Neuse; Christopher B. Walton
- Web page: https://patentgrep.com/patent/US8788986B2

## CPC

- H04L 41/022: Multivendor or multi-standard integration
- G06F 11/3442: {for planning or managing the needed capacity}
- G06F 11/3447: {Performance evaluation by modeling}
- H04L 43/04: Processing captured monitoring data, e.g. for logfile generation
- H04L 67/51: Discovery or management thereof, e.g. service location protocol [SLP] or web services
- G06F 11/3428: {Benchmarking}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A method for expressing a hierarchy of scalabilities in complex systems, including a discrete event simulation and an analytic model, for analysis and prediction of the performance of multi-chip, multi-core, multi-threaded computer processors is provided. Further provided is a capacity planning tool for migrating data center systems from a source configuration which may include source systems with multithreaded, multicore, multichip central processing units to a destination configuration which may include destination systems with multithreaded, multicore and multichip central processing units, wherein the destination systems may be different than the source systems. Apparatus and methods are taught for the assembling of and utilization of linear and exponential scalability factors in the capacity planning tool when a plurality of active processor threads populate processors with multiple chips, multiple cores per chip and multiple threads per core.

## Claims

### Claim 1

A computer-implemented method for determining if a migration to a destination system configuration from a source system configuration is favorable, the method comprising:
receiving a set of CPU performance data from external CPU data repositories;
organizing and storing the set of CPU performance data into an internal data repository;
determining a set of scalability factors, from the set of CPU performance data, comprising a set of linear scalability factors and a set of exponential scalability factors;
calculating a first CPU performance measure for the source system configuration from the set of scalability factors;
calculating a second CPU performance measure for the destination system configuration from the set of scalability factors;
determining an improvement between the first CPU performance measure and the second CPU performance measure;
providing a predetermined criteria based on at least one of the group consisting of CPU utilization and system response time for CPU requests;
determining the migration to the destination system configuration is favorable if the improvement meets the predetermined criteria;
wherein the step of determining the set of scalability factors uses a discrete event simulation process and further comprises:
specifying a set of system parameters;
identifying the set of scalability factors;
executing a simulation process for a predetermined duration;
computing dynamic efficiencies;
computing a set of expected times of completion for a set of tasks;
storing a set of simulation results;
wherein the step of specifying a set of system parameters includes the substeps of:
determining a number of processor chips available to run the set of tasks;
determining a number of cores per processor;
determining a total number of cores;
determining a number of threads per core; and,
determining a total number of available threads.

### Claim 2 (depends on 1)

The method of claim 1 wherein the step of computing a set of expected times of completion for a set of tasks comprises the substeps of:
tracking a number of tasks requesting CPU service in the discrete event simulation process;
dispatching a task in the set of tasks to the discrete event simulation process; and,
computing a delivered thread capacity for the set of tasks.

### Claim 3 (depends on 2)

The method of claim 2 wherein the step of computing a delivered thread capacity for the set of tasks includes the substeps of:
calculating a number of effective elements for an operating system, E1;
calculating a number of effective elements for a processor chip, E2;
calculating a number of effective elements for a processor core, E3;
calculating a number of effective elements for a processor thread, E4;
calculating a number of contending processor chips, C2;
calculating a number of contending cores, C3;
calculating a number of contending threads, C4; and,
computing the delivered thread capacity for a number of active threads Nth assigned to:
delivered
⁢
⁢
thread
⁢
⁢
capacity
=
E
⁢
⁢
1
Nth
×
E
⁢
⁢
2
C
⁢
⁢
2
×
E
⁢
⁢
3
C
⁢
⁢
3
×
E
⁢
⁢
4
C
⁢
⁢
4
.

### Claim 4 (depends on 3)

The method of claim 3 comprising the additional substeps of:
assigning a variable nchips to the number of processor chips available to run the set of tasks;
assigning a variable ncpc to the number of cores per processor;
assigning a variable ncores to the total number of cores;
assigning an index ith to each active task in the set of tasks;
assigning a set of linear variables, L1, L2, L3 and L4 and a set of non-linear variables, a1, a2, a3 and a4 to the set of scalability factors;
calculating a first parameter, ichip, according to
ichip=modulo(ith, nchips);
calculating a second parameter, icore, according to
icore
=
modulo
⁡
(
(
ith
-
ichip
)
nchips
,
ncpc
)
;
defining a first function representative of a number of utilized threads for x CPU chips and y CPU cores:
CT
⁡
(
x
,
y
,
Nth
)
=
Ceiling
⁡
[
Max
⁡
[
0
,
Nth
-
(
y
×
nchips
)
-
x
]
ncores
]
;
defining a second function representative of a number of utilized cores for x CPU chips and y CPU cores:
CC
⁡
(
x
,
y
,
Nth
)
=
∑
jcore
=
0
ncpc
-
1
⁢
Min
⁡
[
CT
⁡
(
x
,
jcore
,
Nth
)
,
1
]
;
defining a third function representative of a number of utilized processors for x CPU chips and y CPU cores:
CP
⁡
(
x
,
y
,
Nth
)
=
∑
jchip
=
0
nchips
-
1
⁢
Min
⁡
[
CC
⁡
(
jchip
,
y
,
Nth
)
,
1
]
;
calculating the number of contending threads according to:
C4=CT(ichip, icore, Nth);
calculating the number of contending cores according to:
C3=CC(ichip, icore, Nth);
calculating the number of contending processors according to:
C2=CP(ichip, icore, Nth);
calculating the number of effective elements for an operating system, according to:
E1=([1+L1*(Nth−1)]*α1^(Nth−1));
calculating the number of effective elements for a processor chip according to:
E2=[1+L2*(C2−1))]×α2^(C2−1);
calculating the number of effective elements for a processor core, according to:
E3=[1+L3*(C3−1))]×α3^(C3−1); and,
calculating the number of effective elements for a processor thread, according to:
E4=[1+L4×(C4−1))]×α4^(C4−1).

### Claim 5

A computer-implemented method for determining if a migration to a destination system configuration from a source system configuration is favorable, the method comprising:
receiving a set of CPU performance data from external CPU data repositories;
organizing and storing the set of CPU performance data into an internal data repository;
determining a set of scalability factors, from the set of CPU performance data, comprising a set of linear scalability factors and a set of exponential scalability factors;
calculating a first CPU performance measure for the source system configuration from the set of scalability factors;
calculating a second CPU performance measure for the destination system configuration from the set of scalability factors;
determining an improvement between the first CPU performance measure and the second CPU performance measure;
providing a predetermined criteria based on at least one of the group consisting of CPU utilization and system response time for CPU requests;
determining the migration to the destination system configuration is favorable if the improvement meets the predetermined criteria;
wherein the step of determining the set of scalability factors uses an analytical modeling process and further comprises:
specifying a set of system parameters;
identifying the set of scalability factors;
computing a set of service rate vectors;
estimating a set of service times;
performing a queuing theory analysis;
calculating an average response time and an average CPU utilization value;
wherein the step of computing a set of service rate vectors comprises the steps:
determining a number of processor chips available to run a set of tasks dispatched on the destination system;
determining a number of cores per processor;
determining a total number of cores;
determining a number of threads per core; and,
determining a maximum number of usable threads.

### Claim 6 (depends on 5)

The method of claim 5 wherein the step of computing a set of service rate vectors further comprises the substeps of:
computing a delivered capacity for each task in the set of tasks; and,
computing a service rate for each task in the set of tasks from the computed delivered capacity.

### Claim 7 (depends on 5)

The method of claim 5 wherein the step of computing service rate vectors further comprises the substeps of:
indexing the set of tasks with a thread index, ith, ranging from 1 (one) to the maximum number of usable threads;
computing the delivered capacity for a task with thread index, ith, an input number of processors, ichip, and an input number of processor cores, icore, as DeliveredCapacity(ichip, icore, ith);
calculating the service rate as ServiceRate(ith) for each thread index according to:
ServiceRate
⁡
(
ith
)
=
∑
ichip
=
0
nchips
-
1
⁢
∑
icore
=
0
ncpc
-
1
⁢
DeliveredCapacity
⁡
(
ichip
,
icore
,
ith
)
,
where nchips is the number of processor chips available to run a set of tasks dispatched on the destination system and where ncpc is the number of cores per processor.

### Claim 8 (depends on 7)

The method of claim 7 wherein the step of computing the delivered capacity for the set of tasks includes the substeps of:
calculating a number of effective elements for an operating system, E1;
calculating a number of effective elements for a processor chip, E2;
calculating a number of effective elements for a processor core, E3;
calculating a number of effective elements for a processor thread, E4;
calculating a number of contending processor chips, C2;
calculating a number of contending cores, C3;
calculating a number of contending threads, C4; and,
computing the delivered thread capacity for a number of active threads Nth assigned to the set of tasks as:
deliveredcapacity
=
E
⁢
⁢
1
Nth
×
E
⁢
⁢
2
C
⁢
⁢
2
×
E
⁢
⁢
3
C
⁢
⁢
3
×
E
⁢
⁢
4
C
⁢
⁢
4
.

### Claim 9 (depends on 8)

The method of claim 8 comprising the additional substeps of:
assigning a variable nchips to the number of processor chips available to run the set of tasks;
assigning a variable ncpc to the number of cores per processor;
assigning a variable ncores to the total number of cores;
assigning an index ith to each active task in the set of tasks;
assigning a set of linear variables, L1, L2, L3 and L4 and a set of non-linear variables, a1, a2, a3 and a4 to the set of scalability factors;
calculating a first parameter, ichip, according to
ichip=modulo(ith, nchips);
calculating a second parameter, icore, according to
icore
=
modulo
⁡
(
(
ith
-
ichip
)
nchips
,
ncpc
)
;
defining a first function representative of a number of utilized threads for x CPU chips and y CPU cores:
CT
⁡
(
x
,
y
,
Nth
)
=
Ceiling
⁡
[
Max
⁡
[
0
,
Nth
-
(
y
×
nchips
)
-
x
]
ncores
]
;
defining a second function representative of a number of utilized cores for x CPU chips and y CPU cores:
CC
⁡
(
x
,
y
,
Nth
)
=
∑
jcore
=
0
ncpc
-
1
⁢
Min
⁡
[
CT
⁡
(
x
,
jcore
,
Nth
)
,
1
]
;
defining a third function representative of a number of utilized processors for x CPU chips and y CPU cores:
CP
⁡
(
x
,
y
,
Nth
)
=
∑
jchip
=
0
nchips
-
1
⁢
Min
⁡
[
CC
⁡
(
jchip
,
y
,
Nth
)
,
1
]
;
calculating the number of contending threads according to:
C4=CT(ichip, icore, Nth);
calculating the number of contending cores according to:
C3=CC(ichip, icore, Nth);
calculating the number of contending processors according to:
C2=CP(ichip, icore, Nth);
calculating the number of effective elements for an operating system, according to:
E1=([1+L1*(Nth−1)]*α1^(Nth−1));
calculating the number of effective elements for a processor chip according to:
E2=[1+L2*(C2−1))]×α2^(C2−1);
calculating the number of effective elements for a processor core, according to:
E3=[1+L3*(C3−1))]×α3^(C3−1); and,
calculating the number of effective elements for a processor thread, according to:
E4=[1+L4×(C4−1))]×α4^(C4−1).