# US 8,788,915 B2 · Apparatuses and methods for encoding using error protection codes > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,788,915 B2 - Document ID: US8788915B2 - Status: Granted - Kind: B2 - Application number: 13/412,539 - Filed: 2012-03-05 - Published: 2013-09-05 - Granted: 2014-07-22 - Earliest claimed: 2012-03-05 - Assignees: Micron Technology, Inc. - Applicants: Stephen P. Van Aken - Inventors: Stephen P. Van Aken - Web page: https://patentgrep.com/patent/US8788915B2 ## CPC - G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)} - G06F 11/1076: {Parity data used in redundant arrays of independent storages, e.g. in RAID systems} - G11C 29/52: Protection of memory contents; Detection of errors in memory contents - H03M 13/15: Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes (H03M13/17 takes precedence) - H03M 13/1515: {Reed-Solomon codes} - H03M 13/152: {Bose-Chaudhuri-Hocquenghem [BCH] codes} - H03M 13/157: {Polynomial evaluation, i.e. determination of a polynomial sum at a given value} - H03M 13/1595: {Parallel or block-wise remainder calculation} - H03M 13/151: {using error location or error correction polynomials} - H03M 13/159: {Remainder calculation, e.g. for encoding and syndrome calculation} - H04L 1/0057: {Block codes (H04L1/0061, H04L1/0064 take precedence)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract Subject matter disclosed herein relates to error protection of data stored in and/or read from a memory device. ## Claims ### Claim 1 An electronically-implemented method of protecting program data, the method comprising: retrieving coefficient data for computation of an error protection code using a canonical form, the computed coefficient data representing coefficients employed to compute parity data from program data, wherein the coefficient data is independent of program data; combining the coefficient data and the program data to compute an error protection code comprising parity data, wherein the parity data comprises a sum of products, wherein the products comprise the coefficient data multiplied by the program data; and storing the program data and the error protection code in memory. ### Claim 2 (depends on 1) The method of claim 1, wherein storing the coefficient data for the error protection code in memory comprises storing in a memory device of a computing system. ### Claim 3 (depends on 1) The method of claim 1, further comprising computing or retrieving the coefficient data responsive to a selection of the error protection code. ### Claim 4 (depends on 3) The method of claim 3, wherein computing or retrieving responsive to the selection of the error protection code comprises computing responsive to the selection of the error protection code by a user. ### Claim 5 (depends on 1) The method of claim 1, further comprising using the stored program data and the stored parity data to correct one or more errors in the stored program data. ### Claim 6 (depends on 1) The method of claim 1, further comprising computing the parity data in parallel. ### Claim 7 (depends on 1) The method of claim 1, further comprising using the computed coefficient data to compute respective parity data for different sets of program data stored in different memory arrays. ### Claim 8 (depends on 1) The method of claim 1, wherein the computed coefficient data is stored in a look-up table. ### Claim 9 (depends on 1) The method of claim 1, wherein the error protection code comprises a generalized block oriented algebraic error protection code. ### Claim 10 (depends on 9) The method of claim 9, wherein the generalized block oriented algebraic error protection code comprises a BCH code or a Reed-Solomon code. ### Claim 11 (depends on 1) The method of claim 1, wherein the canonical coefficients are based, at least in part, on a generator polynomial. ### Claim 12 An apparatus comprising: circuitry configured to compute parity data based, at least in part, on program data and on pre-computed coefficient data representing canonical coefficients for an error protection code, wherein the pre-computed coefficient data are determined independent of the program data, wherein the parity data comprises a sum of products, wherein the products comprise the coefficient data multiplied by the program data; and a memory array configured to store the parity and program data. ### Claim 13 (depends on 12) The apparatus of claim 12, wherein the circuitry comprises circuitry configured to compute the parity data in parallel. ### Claim 14 (depends on 12) The apparatus of claim 12, wherein the circuitry includes an encoder. ### Claim 15 (depends on 12) The apparatus of claim 12, wherein the circuitry includes a decoder. ### Claim 16 (depends on 12) The apparatus of claim 12, wherein the pre-computed coefficient data is stored in a look-up table included in the circuitry. ### Claim 17 (depends on 16) The apparatus of claim 16, wherein the pre-computed coefficient data comprises coefficient data computed external to the apparatus. ### Claim 18 (depends on 12) The apparatus of claim 12, wherein the circuitry comprises combinational logic circuitry. ### Claim 19 (depends on 12) The apparatus of claim 12, wherein the error protection code comprises a selectable error protection code. ### Claim 20 (depends on 19) The apparatus of claim 19, wherein the selectable error protection code comprises one of the following types: a BCH code or a Reed-Solomon code. ### Claim 21 (depends on 12) The apparatus of claim 12, wherein the apparatus comprises at least one of the following: a memory device, a tablet computer, a desktop computer, a laptop computer, a workstation, a server device, a personal digital assistant, a mobile communication device, or any combination thereof. ### Claim 22 An apparatus comprising: parity computing circuit blocks configured to compute associated parity data for corresponding groups of program data, the circuit blocks configured to apply pre-computed coefficients to one or more groups of program data, wherein the pre-computed coefficients are determined independent of the program data, wherein the parity data comprises a sum of products, wherein the products comprise the coefficient data multiplied by the program data; and a memory array configured to store the parity and program data. ### Claim 23 (depends on 22) The apparatus of claim 22, wherein the pre-computed coefficients are independent of the groups of program data. ### Claim 24 (depends on 23) The apparatus of claim 23, wherein the parity computing circuit blocks are configured to operate in parallel.