# US 8,788,909 B2 · Probabilistic error correction in multi-bit-per-cell flash memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,788,909 B2 - Document ID: US8788909B2 - Status: Granted - Kind: B2 - Application number: 12/401,756 - Filed: 2009-03-11 - Published: 2009-08-27 - Granted: 2014-07-22 - Earliest claimed: 2005-10-17 - Assignees: Ramot at Tel-Aviv University Ltd. - Applicants: Simon Litsyn; Idan Alrod; Eran Sharon; Mark Murin; Menahem Lasser - Inventors: Simon Litsyn; Idan Alrod; Eran Sharon; Mark Murin; Menahem Lasser - Web page: https://patentgrep.com/patent/US8788909B2 ## CPC - H03M 13/458: {by updating bit probabilities or hard decisions in an iterative fashion for convergence to a final decoding result} - G06F 11/1012: {using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence)} - G06F 11/1024: {Identification of the type of error} - G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)} - G06F 11/1072: {in multilevel memories} - H03M 13/45: Soft decoding, i.e. using symbol reliability information (H03M13/41 takes precedence) - G11C 11/5642: {Sensing or reading circuits; Data output circuits} - G11C 2029/0409: {Online test} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Data that are stored in cells of a multi-bit-per cell memory, according to a systematic or non-systematic ECC, are read and corrected (systematic ECC) or recovered (non-systematic ECC) in accordance with estimated probabilities that one or more of the read bits are erroneous. In one method of the present invention, the estimates are a priori. In another method of the present invention, the estimates are based only on aspects of the read bits that include significances or bit pages of the read bits. In a third method of the present invention, the estimates are based only on values of the read bits. Not all the estimates are equal. ## Claims ### Claim 1 A method of reading a plurality of data bits that are stored in a memory that includes a plurality of multi-bit cells, the storing being effected by computing a plurality of parity bits that correspond to the data bits and then storing the data bits and the parity bits as stored bits in the cells of the memory, with a respective plurality of the stored bits being stored in each of the cells, the method comprising the steps of: (a) reading the cells, thereby obtaining, for each cell, a respective plurality of read bits; and (b) correcting said read bits that correspond to the data bits in accordance with said read bits that correspond to the parity bits, wherein said correcting is effected in accordance with respective probabilities, of at least two of said read bits being erroneous, that are based at least in part on information obtained as a result of said reading, said information being confined to respective values of said read bits, wherein at least one said probability is different from at least one other said probability, wherein a respective probability of a bit read from a cell being erroneous depends solely on read values of one or more further bits read from the same cell, and wherein the respective probability is derived based on a number of threshold voltage shifts between the read values and one or more possible alternative values. ### Claim 2 A computer-readable storage medium having computer-readable code embodied on the computer-readable storage medium, the computer-readable code for managing a memory that includes a plurality of multi-bit cells and wherein are stored a plurality of data bits, the data bits being stored by computing a plurality of parity bits that correspond to the data bits and then storing the data bits and the parity bits as stored bits in the cells of the memory, with a respective plurality of the stored bits being stored in each of the cells, the computer-readable code comprising: (a) program code for reading the cells, thereby obtaining, for each cell, a respective plurality of read bits; and (b) program code for correcting said read bits that correspond to the data bits in accordance with said read bits that correspond to the parity bits, wherein said correcting is effected in accordance with respective probabilities, of at least two of said read bits being erroneous, that are based at least in part on information obtained as a result of said reading, said information being confined to respective values of said read bits, wherein at least one said probability is different from at least one other said probability, wherein a respective probability of a bit read from a cell being erroneous depends solely on read values of one or more further bits read from the same cell, and wherein the respective probability is derived based on a number of threshold voltage shifts between the read values and one or more possible alternative values. ### Claim 3 A method of reading a plurality of data bits that are stored in a memory that includes a plurality of multi-bit cells, the storing being effected by computing a plurality of protected bits that correspond to the data bits and then storing the protected bits in the cells of the memory, with a respective plurality of the protected bits being stored in each of the cells, the method comprising the steps of: (a) reading the cells, thereby obtaining, for each cell, a respective plurality of read protected bits; and (b) recovering the data bits from the read protected bits, wherein said recovering is effected in accordance with respective probabilities, of at least two of said read protected bits being erroneous, that are based at least in part on information obtained as a result of said reading, said information being confined to respective values of said read protected bits, wherein at least one said probability is different from at least one other said probability, wherein a respective probability of a protected bit read from a cell being erroneous depends solely on read values of one or more further protected bits read from the same cell, and wherein the respective probability is derived based on a number of threshold voltage shifts between the read values and one or more possible alternative values. ### Claim 4 A computer-readable storage medium having computer-readable code embodied on the computer-readable storage medium, the computer-readable code for managing a memory that includes a plurality of multi-bit cells and wherein are stored a plurality of data bits, the data bits being stored by computing a plurality of protected bits that correspond to the data bits and then storing the protected bits in the cells of the memory, with a respective plurality of the protected bits being stored in each of the cells, the computer-readable code comprising: (a) program code for reading the cells, thereby obtaining, for each cell, a respective plurality of read protected bits; and (b) program code for recovering the data bits from said read protected bits, wherein said recovering is effected in accordance with respective probabilities, of at least two of said read protected bits being erroneous, that are based at least in part on information obtained as a result of said reading, said information being confined to respective values of said read protected bits, wherein at least one said probability is different from at least one other said probability, wherein a respective probability of a protected bit read from a cell being erroneous depends solely on read values of one or more further protected bits read from the same cell, and wherein the respective probability is derived based on a number of threshold voltage shifts between the read values and one or more possible alternative values. ### Claim 5 An apparatus comprising a memory, the memory comprising plurality of memory cells, wherein the apparatus is configured to read a plurality of data bits stored on the memory, the storing being effected by computing a plurality of parity bits that correspond to the data bits and then storing the data bits and the parity bits as stored bits in the cells of the memory, with a respective plurality of the stored bits being stored in each of the cells, by at least: (a) reading the cells, thereby obtaining, for each cell, a respective plurality of read bits; and (b) correcting said read bits that correspond to the data bits in accordance with said read bits that correspond to the parity bits, wherein said correcting is effected in accordance with respective probabilities, of at least two of said read bits being erroneous, that are based at least in part on information obtained as a result of said reading, said information being confined to respective values of said read bits, wherein at least one said probability is different from at least one other said probability, wherein a respective probability of a bit read from a cell being erroneous depends solely on read values of one or more further bits read from the same cell, and wherein the respective probability is derived based on a number of threshold voltage shifts between the read values and one or more possible alternative values. ### Claim 6 (depends on 5) The apparatus of claim 5, wherein the apparatus further comprises a controller and wherein the controller is configured to read the plurality of data bits stored on the memory.