# US 8,788,908 B2 · Data storage system having multi-bit memory device and on-chip buffer program method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,788,908 B2 - Document ID: US8788908B2 - Status: Granted - Kind: B2 - Application number: 13/225,676 - Filed: 2011-09-06 - Published: 2012-11-15 - Granted: 2014-07-22 - Earliest claimed: 2011-05-11 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Sangyong Yoon; Kitae Park - Inventors: Sangyong Yoon; Kitae Park - Web page: https://patentgrep.com/patent/US8788908B2 ## CPC - G06F 11/1072: {in multilevel memories} - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G11C 11/5642: {Sensing or reading circuits; Data output circuits} - G11C 2029/0411: {Online error correction} - G11C 2211/5641: Multilevel memory having cells with different number of storage levels - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A data storage device includes a multi-bit memory device including a memory cell array, the memory cell array including a first memory region and a second memory region, and a memory controller including a buffer memory and configured to control the multi-bit memory device. The memory controller is configured to control the multi-bit memory device to execute a buffer program operation in which data stored in the buffer memory is stored in the first memory region, and to control the multi-bit memory device to execute a main program operation in which the data stored in the first memory region is stored in the second memory region. The memory controller is further configured to generate parity data based upon the data stored to the first region, the parity data being copied from the first memory region to the second memory region via the main program operation. ## Claims ### Claim 1 A data storage device comprising: a multi-bit memory device including a memory cell array, the memory cell array including a first memory region and a second memory region; and a memory controller including a buffer memory and configured to control the multi-bit memory device, wherein the memory controller is configured to control the multi-bit memory device to execute a buffer program operation in which data stored in the buffer memory is stored in the first memory region, wherein the memory controller is further configured to control the multi-bit memory device to execute a main program operation in which the data stored in the first memory region is stored in the second memory region, and wherein the memory controller is further configured to generate parity data based upon the data stored to the first memory region, and to store the parity data in the first memory region, the parity data being copied from the first memory region to the second memory region via the main program operation. ### Claim 2 (depends on 1) The data storage device of claim 1, wherein the first memory region is formed of memory cells each storing 1-bit data, and the second memory region is formed of memory cells each storing M-bit data, where M is an integer of 3 or more. ### Claim 3 (depends on 2) The data storage device of claim 2, wherein a size of the parity data is determined on the basis of a read protocol of the second memory region. ### Claim 4 (depends on 3) The data storage device of claim 3, wherein the memory controller is configured to execute the buffer program operation when data corresponding to a minimum program unit of the first memory region is stored in the buffer memory, and to executed the main program operation when data corresponding to a minimum program unit of the second memory region is stored in the first memory region. ### Claim 5 A data storage device comprising: a multi-bit memory device including a memory cell array, the memory cell array including a first memory region and a second memory region; and a memory controller including a buffer memory and configured to control the multi-bit memory device, wherein the memory controller is configured to control the multi-bit memory device to execute a buffer program operation in which data stored in the buffer memory is stored in the first memory region, wherein the memory controller is further configured to control the multi-bit memory device to execute a main program operation in which the data stored in the first memory region is stored in the second memory region, wherein the memory controller is further configured to generate parity data based upon the data stored to the first memory region, and to store the parity data in the first memory region, the parity data being copied from the first memory region to the second memory region via the main program operation, and wherein the main program operation includes a course program operation, a fine program operation, a single-bit read operation of reading data from the first memory region and a multi-bit program operation of storing data read from the first memory region in the second memory region, the single-bit read operation being repeated according to the main program operation. ### Claim 6 (depends on 5) The data storage device of claim 5, wherein the main program operation further includes a data output operation in which data read via the single-bit read operation is sent to the memory controller for error detection and correction. ### Claim 7 An on-chip buffer program method of a data storage device which includes a multi-bit memory device having a memory cell array, and a memory controller having a buffer memory and configured to control the multi-bit memory device, the on-chip buffer program method comprising: executing a buffer program operation when data corresponding to a minimum program unit of a first region of the memory cell array is stored in the buffer memory; and executing a main program operation when data corresponding to a minimum program unit of a second region of the memory cell array is stored in the first region, wherein the buffer program operation includes generating parity data based upon data transferred to the first region and storing the parity data in the first region, and the main program operation includes copying the parity data from the first region to the second region. ### Claim 8 (depends on 7) The on-chip buffer program operation of claim 7, wherein the first region is formed of memory cells each storing 1-bit data and the second region is formed of memory cells each storing M-bit data, M being an integer of 3 or more. ### Claim 9 (depends on 7) The on-chip buffer program operation of claim 7, wherein a size of the parity data is determined on the basis of a read protocol of the second region. ### Claim 10 (depends on 9) The on-chip buffer program operation of claim 9, wherein the main program operation includes at least one of a 1-step program operation, a coarse program operation, and a fine program operation. ### Claim 11 (depends on 10) The on-chip buffer program operation of claim 10, wherein the main program operation includes a single-bit read operation of reading data from the first region and a multi-bit program operation of storing data read from the first region in the second region, the single-bit read operation being repeated according to the main program operation. ### Claim 12 (depends on 11) The on-chip buffer program operation of claim 11, wherein the main program operation includes a data output operation in which data read via the single-bit read operation is sent to the memory controller for error detection and correction.