# US 8,788,904 B2 · Methods and apparatus to perform error detection and correction

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- Number: US 8,788,904 B2
- Document ID: US8788904B2
- Status: Granted
- Kind: B2
- Application number: 13/285,742
- Filed: 2011-10-31
- Published: 2013-05-02
- Granted: 2014-07-22
- Earliest claimed: 2011-10-31
- Assignees: Hewlett-Packard Development Company, L.P.
- Applicants: Sheng Li; Norman Paul Jouppi; Naveen Muralimanohar
- Inventors: Sheng Li; Norman Paul Jouppi; Naveen Muralimanohar
- Web page: https://patentgrep.com/patent/US8788904B2

## CPC

- G06F 11/1064: {in cache or content addressable memories}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Example methods, apparatus, and articles of manufacture to perform error detection and correction are disclosed. A disclosed example method involves enabling a memory controller to operate in one of a tagged memory mode or a non-tagged memory mode. In addition, when the tagged memory mode is enabled in the memory controller, a five-error-correction-six-error-detection per-burst mode is selected to perform error correction on data. When the non-tagged memory mode is enabled in the memory controller, one of a six-error-correction-seven-error-detection per-burst mode or a single-error-correction-dual-error-detection per-transfer mode is selected based on a pattern of error types in the data.

## Claims

### Claim 1

A method to perform error detection and correction, the method comprising:
dynamically enabling a memory controller, that is operable in both a tagged memory mode and a non-tagged memory mode, to operate exclusively in the tagged memory mode or exclusively in the non-tagged memory mode based on a setting in a system memory mode register of the memory controller;
when the tagged memory mode is enabled in the memory controller, selecting a five-error-correction-six-error-detection per-burst mode to perform error correction on data; and
when the non-tagged memory mode is enabled in the memory controller, selecting one of a six-error-correction-seven-error-detection per-burst mode or a single-error-correction-dual-error-detection per-transfer mode based on a pattern of error types in the data.

### Claim 2 (depends on 1)

A method as defined in claim 1, further comprising, when the tagged memory mode is enabled in the memory controller, retrieving a number of bytes of data, a number of bits of an error correction code, and extension bits corresponding to a tagged extended double word from a non-tag-specific memory into the memory controller within a single read cycle.

### Claim 3 (depends on 1)

A method as defined in claim 1, further comprising, when the tagged memory mode is enabled in the memory controller:
using a fast error correction code process to correct an error when the memory controller detects one error in the data or extension bits;
using a slow error correction code process to correct errors when the memory controller detects two or three errors in the data or the extension bits; and
using a slowest error correction code process to correct errors when the memory controller detects more than three errors in the data or the extension bits.

### Claim 4 (depends on 1)

A method as defined in claim 1, further comprising, when the tagged memory mode is enabled in the memory controller, using a first portion of bits reserved for an error correction code to store extension bits for tagged memory words, and using a second portion of the bits reserved for the error correction code to store the error correction code.

### Claim 5 (depends on 4)

A method as defined in claim 4, wherein the first portion of the bits reserved for the error correction code includes eight bits corresponding to sixty-four-bit words, and wherein the second portion of the bits reserved for the error correction code includes fifty-one bits corresponding to the sixty-four-bit words.

### Claim 6

An apparatus to perform error detection and correction, the apparatus comprising:
a tagged mode selector to dynamically enable a memory controller to operate in a tagged memory mode based on a first setting in a system memory mode register of the memory controller, and to dynamically enable the memory controller to operate in the non-tagged memory mode based on a second setting in a system memory mode register of the memory controller; and
an error correction mode selector to:
select a fast error correction code process to correct an error when the memory controller detects one error in data or extension bits;
select a slow error correction code process to correct errors when the memory controller detects two or three errors in the data or the extension bits;
select a slowest error correction code process to correct errors when the memory controller detects more than three errors in the data or the extension bits; and
select one of a six-error-correction-seven-error-detection per-burst mode or a single-error-correction-dual-error-detection per-transfer mode based on error types in the data when the tagged mode selector enables a non-tagged memory mode in the memory controller.

### Claim 7 (depends on 6)

An apparatus as defined in claim 6, wherein the error correction mode selector is to select a five-error-correction-six-error-detection per-burst mode to perform error correction on the data or the extension bits.

### Claim 8 (depends on 6)

An apparatus as defined in claim 6, further comprising logic to perform a fast error correction code process, a slow error correction code process, or a slowest error correction code process on the data and the extension bits retrieved from a non-tag-specific memory.

### Claim 9

A non-transitory machine accessible storage medium comprising instructions that, when executed, cause a machine to at least:
enable a memory controller to operate in one of a tagged memory mode or a non-tagged memory mode;
when the tagged memory mode is enabled in the memory controller, select a five-error-correction-six-error-detection mode to perform error correction on data or extension bits; and
when the non-tagged memory mode is enabled in the memory controller, select, based on a pattern of previously detected error types in previous data or previous extension bits, one of a six-error-correction-seven-error-detection mode or a single-error-correction-dual-error-detection mode.

### Claim 10 (depends on 9)

A non-transitory machine accessible storage medium as defined in claim 9, wherein the instructions cause the memory controller to operate in one of the tagged memory mode or the non-tagged memory mode based on a setting in a system memory mode register of the memory controller.

### Claim 11 (depends on 9)

A non-transitory machine accessible storage medium as defined in claim 9, wherein the instructions further cause the machine to, when the tagged memory mode is enabled in the memory controller, use a first portion of bits reserved for an error correction code to store extension bits for tagged memory words, and use a second portion of the bits reserved for the error correction code to store a number of error correction code bits corresponding to the tagged memory words.

### Claim 12 (depends on 11)

A non-transitory machine accessible storage medium as defined in claim 11, wherein the instructions further cause the machine to:
use a fast error correction code process to correct an error when the memory controller detects one error in the data or extension bits;
use a slow error correction code process to correct errors when the memory controller detects two or three errors in the data or the extension bits; and
use a slowest error correction code process to correct errors when the memory controller detects more than three errors in the data or the extension bits.