# US 8,788,893 B2 · Semiconductor device and memory device

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- Number: US 8,788,893 B2
- Document ID: US8788893B2
- Status: Granted
- Kind: B2
- Application number: 13/596,975
- Filed: 2012-08-28
- Published: 2014-03-06
- Granted: 2014-07-22
- Earliest claimed: 2012-08-28
- Assignees: SK hynix Inc.
- Applicants: Kwanweon Kim; Hyunsu Yoon; Jeongtae Hwang
- Inventors: Kwanweon Kim; Hyunsu Yoon; Jeongtae Hwang
- Web page: https://patentgrep.com/patent/US8788893B2

## CPC

- G11C 29/46: Test trigger logic
- G11C 16/00: Erasable programmable read-only memories (G11C14/00 takes precedence)
- G11C 2029/4402: {Internal storage of test result, quality data, chip identification, repair information}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory device includes a command decoder for generating a test selection code and a test setup data by decoding an external command and an external address, a non-volatile memory for storing an internal setup data, a counter for generating an internal selection code by counting a clock, a first selector for selecting the test selection code during a test mode operation, selecting the internal selection code during a boot-up operation, and transferring the selected selection code through a selection code transfer bus, a second selector for selecting the test setup data during the test mode operation, selecting the internal setup data that is outputted from the non-volatile memory during the boot-up operation, and transferring the selected selection code through a setup data transfer bus; and setup circuits for performing a setup operation based on the information transferred through the selection code transfer bus and the setup data transfer bus.

## Claims

### Claim 1

A memory device, comprising: a command decoder configured to generate a test selection code and a test setup data by decoding an external command and an external address; a non-volatile memory configured to store an internal setup data; a counter configured to generate an internal selection code by counting a clock; a first selector configured to select the test selection code during a test mode operation, select the internal selection code during a boot-up operation, and transfer the selected selection code through a selection code transfer bus; a second selector configured to select the test setup data during the test mode operation, select the internal setup data that is outputted from the non-volatile memory during the boot-up operation, and transfer the selected setup data through the setup data transfer bus; and a plurality of setup circuits configured to perform a setup operation based on the information transferred through the selection code transfer bus and the setup data transfer bus.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the clock is synchronized with the internal setup data that is outputted from the non-volatile memory.

### Claim 3 (depends on 1)

The memory device of claim 1, wherein a setup circuit selected based on the selection code that is transferred through the selection code transfer bus among the multiple setup circuits receives a setup data that is transferred through the setup data transfer bus.

### Claim 4 (depends on 1)

The memory device of claim 1, wherein each of the setup circuits includes:
a selection code decoding unit for generating an enable signal by decoding a selection code that is transferred through the selection code transfer bus;
a latch unit for storing a setup data that is transferred through the setup data transfer bus when the signal is enabled; and
a setup unit for performing a setup operation based on the setup data stored in the latch unit.

### Claim 5 (depends on 1)

The memory device of claim 1, wherein each of the selection code transfer bus and the setup data transfer bus includes a plurality of lines.

### Claim 6 (depends on 1)

The memory device of claim 1, wherein the non-volatile memory include an e-fuse array.

### Claim 7

A semiconductor device, comprising: a decoder configured to generate a test selection code and a test setup data by decoding an external input signal; a non-volatile memory configured to store an internal setup data; a counter configured to generate an internal selection code by counting a clock; a first selector configured to select the test selection code during a test mode operation, select the internal selection code during a boot-up operation, and transfer the selected selection code through a selection code transfer bus; a second selector configured to select the test setup data during the test mode operation, select the internal setup data that is outputted from the non-volatile memory during the boot-up operation, and transfer the selected setup data through the setup data transfer bus; and a plurality of setup circuits configured to perform a setup operation based on the information transferred through the selection code transfer bus and the setup data transfer bus.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the clock is synchronized with the internal setup data that is outputted from the non-volatile memory.