# US 8,788,891 B2 · Bitline deletion

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- Number: US 8,788,891 B2
- Document ID: US8788891B2
- Status: Granted
- Kind: B2
- Application number: 13/523,633
- Filed: 2012-06-14
- Published: 2013-12-19
- Granted: 2014-07-22
- Earliest claimed: 2012-06-14
- Assignees: International Business Machines Corporation
- Applicants: Ekaterina M. Ambroladze; Michael A. Blake; Michael Fee; Hieu T. Huynh; Patrick J. Meaney; Arthur J. O'Neill
- Inventors: Ekaterina M. Ambroladze; Michael A. Blake; Michael Fee; Hieu T. Huynh; Patrick J. Meaney; Arthur J. O'Neill
- Web page: https://patentgrep.com/patent/US8788891B2

## CPC

- G06F 11/1064: {in cache or content addressable memories}
- G06F 11/073: {in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00)}
- G06F 11/076: {by exceeding a count or rate limit, e.g. word- or bit count limit}
- G06F 11/08: Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G11C 2029/1204: {Bit line control}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Embodiments relate to a method including detecting a first error when reading a first cache line, recording a first address of the first error, detecting a second error when reading a second cache line and recording a second address of the second error. Embodiments also include comparing the first and second bitline address, comparing the first and second wordline address, activating a bitline delete mode based on matching first and second bitline addresses and not matching the first and second wordline addresses, detecting a third error when reading a third cache line, recording a third bitline address of the third error, comparing the second bitline address to a third bitline address and deleting a location corresponding to the third cache line from available cache locations based on the activated bitline delete mode and the third bitline address matching the second bitline address.

## Claims

### Claim 1

A method for bitline deletion, the method comprising:
detecting a first error when reading a first cache line in an array within a cache;
recording a first bitline address and a first wordline address of the first error in the first cache line;
detecting a second error when reading a second cache line in the array within the cache;
recording a second bitline address and a second wordline address of the second error in the second cache line;
comparing the first bitline address to the second bitline address;
comparing the first wordline address to the second wordline address;
activating, by a cache controller, a bitline delete mode based on the first bitline address matching the second bitline address and the first wordline address not matching the second wordline address;
detecting a third error when reading a third cache line in the array within the cache;
recording a third bitline address of the third error in the third cache line;
comparing the second bitline address to the third bitline address of the third cache line; and
removing, by the cache controller, a location corresponding to the third cache line from available cache locations based on the bitline delete mode being activated and the third bitline address matching the second bitline address.

### Claim 2 (depends on 1)

The method of claim 1, wherein activating, by the cache controller, the bitline delete mode comprises:
incrementing a bitline error counter based on the first bitline address matching the second bitline address and the first wordline address not matching the second wordline address; and
activating the bitline delete mode based on the bitline error counter being greater than or equal to a bitline delete threshold.

### Claim 3 (depends on 2)

The method of claim 2, wherein the bitline error counter is reset based on a non-matching result from the comparing of the second bitline address to the third bitline address.

### Claim 4 (depends on 2)

The method of claim 2, wherein incrementing, by the cache controller, the bitline error counter comprises setting a bitline error seen latch and wherein the bitline delete threshold comprises a static threshold that changes a value of the bitline error seen latch.

### Claim 5 (depends on 1)

The method of claim 1, wherein removing, by the cache controller, the location corresponding to the third cache line from available cache locations comprises removing the location regardless of a wordline address of the third cache line.

### Claim 6 (depends on 1)

The method of claim 1, wherein removing, by the cache controller, the location corresponding to the third cache line from available cache locations comprises removing a section of the cache from a cache directory, the section including a plurality of lines including the third cache line.

### Claim 7 (depends on 1)

The method of claim 1, wherein the first error, second error and third error are consecutive cache line read errors.

### Claim 8 (depends on 1)

The method of claim 1, comprising copying the third cache line from the cache to a higher level memory located further from a processor coupled to the cache.