# US 8,788,889 B2 · Bit stream aliasing in memory system with probabilistic decoding > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,788,889 B2 - Document ID: US8788889B2 - Status: Granted - Kind: B2 - Application number: 13/304,272 - Filed: 2011-11-23 - Published: 2013-05-23 - Granted: 2014-07-22 - Earliest claimed: 2011-11-23 - Assignees: SanDisk Technologies LLC - Applicants: Seungjune Jeon; Steven Cheng - Inventors: Seungjune Jeon; Steven Cheng - Web page: https://patentgrep.com/patent/US8788889B2 ## CPC - G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature} - G06F 13/14: Handling requests for interconnection or transfer - H04L 1/0061: {Error detection codes} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract An aliasing module is defined and connected to receive a first bit stream to be transmitted over a data bus from a memory to an external controller of the memory. The aliasing module is defined and connected to alias the first bit stream as a second bit stream and transmit the second bit stream over the data bus in lieu of the first bit stream. A de-aliasing module is defined and connected to receive the second bit stream from the data bus at the external controller. The de-aliasing module is defined and connected to de-alias the received second bit stream back to the first bit stream and provide the first bit stream to the external controller for processing. ## Claims ### Claim 1 A system for bit stream aliasing in a memory system, comprising: an aliasing module defined and connected to receive a first bit stream to be transmitted over a data bus from a memory to an external controller of the memory, the aliasing module defined and connected to alias the first bit stream as a second bit stream and transmit the second bit stream over the data bus in lieu of the first bit stream; and a de-aliasing module defined and connected to receive the second bit stream from the data bus at the external controller, the de-aliasing module defined and connected to de-alias the received second bit stream back to the first bit stream and provide the first bit stream to the external controller for processing. ### Claim 2 (depends on 1) The system as recited in claim 1, wherein the aliasing module is defined and connected to receive the first bit stream from a data register of the memory. ### Claim 3 (depends on 1) The system as recited in claim 1, wherein the aliasing module is defined as separate circuitry external to the memory. ### Claim 4 (depends on 1) The system as recited in claim 1, wherein the aliasing module is defined as circuitry internal to the memory. ### Claim 5 (depends on 1) The system as recited in claim 1, wherein the de-aliasing module is defined and connected to provide the first bit stream to an error correction code decoder within the external controller of the memory. ### Claim 6 (depends on 1) The system as recited in claim 1, wherein the de-aliasing module is defined as separate circuitry external to the external controller. ### Claim 7 (depends on 1) The system as recited in claim 1, wherein the de-aliasing module is defined as circuitry internal to the external controller. ### Claim 8 (depends on 1) The system as recited in claim 1, wherein the aliasing module is defined to be programmed with data specifying an identity of the first bit stream, and with data specifying an identity of the second bit stream, and with data specifying an aliasing enablement condition. ### Claim 9 The system as recited in claim, wherein the aliasing module is hard-wired to alias the first bit stream as the second bit stream each time the first bit stream is to be transmitted over the data bus from the memory to the external controller. ### Claim 10 (depends on 1) The system as recited in claim 1, wherein the de-aliasing module is defined to be programmed with data specifying an identity of the first bit stream, and with data specifying an identity of the second bit stream, and with data specifying a de-aliasing enablement condition. ### Claim 11 (depends on 1) The system as recited in claim 1, wherein the de-aliasing module is hard-wired to de-alias the second bit stream back to the first bit stream each time the second bit stream is received from the data bus at the external controller. ### Claim 12 (depends on 5) The system as recited in claim 5, wherein the first bit stream is a more frequently transmitted bit stream from the memory to the external controller, and wherein the second bit stream is more reliably decoded by the error correction code decoder at the external controller as compared to the first bit stream. ### Claim 13 (depends on 12) The system as recited in claim 12, wherein the first bit stream is associated with a non-monotonically varying probability of received bit stream error occurrence as a function of storage element threshold voltage level, and wherein the second bit stream is associated with a monotonically varying probability of received bit stream error occurrence as a function of storage element threshold voltage level. ### Claim 14 (depends on 12) The system as recited in claim 12, wherein the second bit stream corresponds to a transmitted bit stream that maps to a lower number of received bit streams in which a probability of hard bit error is equal to a dominant probability term. ### Claim 15 A memory system, comprising: a memory array; a data register defined and connected to receive and store a first bit stream from the memory array; an aliasing module defined and connected to receive the first bit stream from the data register and alias the first bit stream as a second bit stream, the aliasing module defined and connected to transmit the second bit stream in lieu of the first bit stream; a data bus connected to receive the second bit stream transmitted from the aliasing module; a de-aliasing module connected to receive the second bit stream transmitted over the data bus from the aliasing module and de-alias the second bit stream back to the first bit stream; and an external controller including an error correction code decoder connected to receive the first bit stream from the de-aliasing module. ### Claim 16 (depends on 15) The memory system of claim 15, wherein the memory system is a flash memory system. ### Claim 17 (depends on 15) The memory system of claim 15, wherein the aliasing module is hard-wired to alias the first bit stream as the second bit stream each time the first bit stream is to be transmitted over the data bus, and wherein the de-aliasing module is hard-wired to de-alias the second bit stream back to the first bit stream each time the second bit stream is received from the data bus. ### Claim 18 (depends on 15) The memory system of claim 15, wherein each of the aliasing and de-aliasing modules is defined to be programmed with data specifying an identity of the first bit stream, and with data specifying an identity of the second bit stream, and with data specifying an aliasing and de-aliasing enablement condition. ### Claim 19 (depends on 15) The memory system of claim 15, wherein the first bit stream is a more frequently transmitted bit stream from the memory array to the external controller, and wherein the second bit stream is more reliably decoded by the error correction code decoder at the external controller as compared to the first bit stream. ### Claim 20 A method for operating a memory system, comprising: reading a first bit stream from a storage element in a memory array; aliasing the first bit stream as a second bit stream; transmitting the second bit stream over a data bus to an external memory controller in lieu of the first bit stream; de-aliasing the second bit stream back to the first bit stream upon arrival of the second bit stream at the external memory controller; and providing the first bit stream to an error correction code decoder at the external memory controller. ### Claim 21 (depends on 20) The method as recited in claim 20, wherein the first bit stream is a more frequently transmitted bit stream from the memory to the external controller, and wherein the second bit stream is more reliably decoded by the error correction code decoder at the external controller as compared to the first bit stream. ### Claim 22 (depends on 21) The method as recited in claim 21, wherein the first bit stream is associated with a non-monotonically varying probability of received bit stream error occurrence as a function of storage element threshold voltage level, and wherein the second bit stream is associated with a monotonically varying probability of received bit stream error occurrence as a function of storage element threshold voltage level. ### Claim 23 (depends on 21) The method as recited in claim 21, wherein the second bit stream corresponds to a transmitted bit stream that maps to a lower number of received bit streams in which a probability of hard bit error is equal to a dominant probability term. ### Claim 24 (depends on 20) The method as recited in claim 20, further comprising: programming the aliasing module with data specifying an identity of the first bit stream, and with data specifying an identity of the second bit stream, and with data specifying an aliasing enablement condition. ### Claim 25 (depends on 20) The method as recited in claim 20, further comprising: programming the de-aliasing module with data specifying an identity of the first bit stream, and with data specifying an identity of the second bit stream, and with data specifying a de-aliasing enablement condition.