# US 8,788,862 B1 · Method and system for efficiently transitioning a communication circuit from a low-power state

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 8,788,862 B1
- Document ID: US8788862B1
- Status: Granted
- Kind: B1
- Application number: 13/175,745
- Filed: 2011-07-01
- Granted: 2014-07-22
- Earliest claimed: 2011-07-01
- Assignees: Altera Corporation
- Applicants: Divya Vijayaraghavan; Chong H. Lee
- Inventors: Divya Vijayaraghavan; Chong H. Lee
- Web page: https://patentgrep.com/patent/US8788862B1

## CPC

- G06F 1/3278: {Power saving in modem or I/O interface}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- Y02D 30/50: in wire-line communication networks, e.g. low power modes or reduced link rate
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A method and system for efficiently transitioning a communication circuit from a low-power state are disclosed. A first device and second device in a low-power state may be transitioned to an active state to enable the transmission of data over a communication link, where energy consumption of one or more components of the first and/or second devices may be reduced in the low-power state. The transition may be initiated by the first device responsive to a signal and/or an expiration of a timer. Responsive thereto, a scrambler of the first device may be temporarily bypassed to accelerate achieving block lock at the second device, thereby enabling the system to more quickly transition from the low-power state to the active state.

## Claims

### Claim 1

A method of efficiently transitioning a communication circuit from a low-power state, said method comprising:
responsive to an event, activating a transmitter of a first device;
transmitting, over a communication link, an alert signal for reception by a second device;
bypassing a scrambler of said first device to accelerate block lock at said second device; and
reactivating at least one component of said first device to transition from said low-power state to an active state.

### Claim 2 (depends on 1)

The method of claim 1, wherein said communication link is operable to provide a communication path between said first and second devices, and wherein said alert signal is operable to initiate a reactivation of a receiver of said second device.

### Claim 3 (depends on 1)

The method of claim 1, wherein said first device is a programmable logic device.

### Claim 4 (depends on 1)

The method of claim 1, wherein said bypassing said scrambler is performed using a multiplexer, and wherein said bypassing enables said transition from said low-power state to said active state to be performed more quickly than without said bypassing.

### Claim 5 (depends on 1)

The method of claim 1, wherein said scrambler is implemented in an encoder of a forward error correction sublayer of said first device.

### Claim 6 (depends on 1)

The method of claim 1 further comprising:
responsive to detecting block lock at said second device, reinserting said scrambler in a data path of said first device.

### Claim 7 (depends on 1)

The method of claim 1 further comprising:
requesting bypass of a descrambler of said second device to accelerate block lock at said second device; and
responsive to detecting block lock at said second device, requesting reinsertion of said scrambler in a data path of said second device.

### Claim 8 (depends on 1)

The method of claim 1, wherein said event is selected from a group consisting of: a detection of a signal associated with data transmission over said communication link; and an expiration of a timer associated with a period of reduced data transmission over said communication link.

### Claim 9

A circuit of a first device, said circuit comprising:
a first component operable to scramble data to be transmitted over a communication link, wherein said communication link provides a communication path between said first device and a second device; and
a second component operable to bypass said first component to accelerate block lock at said second device, and wherein said second component is further operable to bypass said first component responsive to an event associated with a transition from a low-power state to an active state.

### Claim 10 (depends on 9)

The circuit of claim 9, wherein said first device is a programmable logic device.

### Claim 11 (depends on 9)

The circuit of claim 9, wherein said second component comprises a multiplexer.

### Claim 12 (depends on 9)

The circuit of claim 9, wherein said second component is further operable to bypass said first component to enable said transition from said low-power state to said active state to be performed more quickly than without bypassing of said first component.

### Claim 13 (depends on 9)

The circuit of claim 9, wherein said second component is further operable to reinsert said first component in a data path of said first device responsive to detecting block lock at said second device.

### Claim 14 (depends on 9)

The circuit of claim 9 further comprising:
a third component operable to generate a sequence, and
wherein said first component is further operable to utilize said sequence to scramble said data.

### Claim 15 (depends on 9)

The circuit of claim 9, wherein said event is selected from a group consisting of: a detection of a signal associated with data transmission over said communication link; and an expiration of a timer associated with a period of reduced data transmission over said communication link.

### Claim 16

An integrated circuit comprising:
a transmitter operable to communicate with another device over a communication link;
a data scrambler operable to scramble data to be transmitted by said transmitter; and
a scrambler bypass module operable to bypass said first component to accelerate block lock at said another device, and wherein said scrambler bypass module is further operable to bypass said data scrambler responsive to an event associated with a transition from a low-power state to an active state.

### Claim 17 (depends on 16)

The programmable logic device of claim 16, wherein said data scrambler is a programmable logic device.

### Claim 18 (depends on 16)

The programmable logic device of claim 16, wherein said scrambler bypass module comprises a multiplexer.

### Claim 19 (depends on 16)

The programmable logic device of claim 16, wherein said scrambler bypass module is further operable to bypass said data scrambler to enable said transition from said low-power state to be performed more quickly than without bypassing of said data scrambler.

### Claim 20 (depends on 16)

The programmable logic device of claim 16, wherein said scrambler bypass module is further operable to reinsert said data scrambler in a data path of said first device responsive to detecting block lock at said second device.

### Claim 21 (depends on 16)

The programmable logic device of claim 16, wherein said forward error correction sublayer further comprises another component operable to generate a sequence, and wherein said data scrambler is further operable to utilize said sequence to scramble said data.

### Claim 22 (depends on 16)

The programmable logic device of claim 16, wherein said event is selected from a group consisting of: a detection of a signal associated with data transmission over said communication link; and an expiration of a timer associated with a period of reduced data transmission over said communication link.