# US 8,788,793 B2 · Instruction issue to plural computing units from plural stream buffers based on priority in instruction order table > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,788,793 B2 - Document ID: US8788793B2 - Status: Granted - Kind: B2 - Application number: 13/320,668 - Filed: 2010-05-18 - Published: 2012-03-08 - Granted: 2014-07-22 - Earliest claimed: 2009-05-18 - Assignees: Panasonic Corporation - Applicants: Hiroyuki Morishita - Inventors: Hiroyuki Morishita - Web page: https://patentgrep.com/patent/US8788793B2 ## CPC - G06F 9/3851: {from multiple instruction streams, e.g. multistreaming} - G06F 9/3889: {controlled by multiple instructions, e.g. MIMD, decoupled access or execute} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A processor including L computing units, L being an integer of 2 or greater, the processor comprising: an instruction buffer including M×Z instruction storage areas each storing one instruction, M instruction streams being input in a state of being distinguished from each other, each of the M instruction streams including Z instructions, M and Z each being an integer of 2 or greater, M×Z being equal to or greater than L; an order information holding unit holding order information that indicates an order of the M×Z instruction storage areas; an extraction unit operable to extract instructions from the M×Z instruction storage areas; and a control unit operable to cause the extraction unit to extract L instructions in executable state from the M×Z instruction storage areas in accordance with the order indicated by the order information, and input the instructions into different ones of the L computing units. ## Claims ### Claim 1 A processor including L computing units, L being an integer of 2 or greater, the processor comprising: an instruction buffer including M×Z instruction storage areas each storing one instruction, M instruction streams being input in a state of being distinguished from each other, each of the M instruction streams including Z instructions, M being an integer of 2 or greater, Z being an integer of 2 or greater, M×Z being equal to or greater than L; an order information holding unit holding M×Z pieces of order information that indicate an order of the M×Z instruction storage areas of the instruction buffer; an extraction unit operable to extract instructions from the M×Z instruction storage areas of the instruction buffer; and a control unit operable to cause the extraction unit to extract L instructions in executable state from the M×Z instruction storage areas in accordance with the order indicated by the order information held by the order information holding unit, and input the extracted L instructions into different ones of the L computing units. ### Claim 2 (depends on 1) The processor of claim 1, wherein the instruction buffer includes M×Z flags that correspond one-to-one to the M×Z instruction storage areas and each indicate whether or not an instruction stored in a corresponding instruction storage area is executable, and the control unit recognizes all instructions that are in executable state by referring to the M×Z flags. ### Claim 3 (depends on 1) The processor of claim 1, wherein one of the M instruction streams is a performance-guarantee instruction stream that is required to guarantee completing a process within a predetermined time period. ### Claim 4 (depends on 3) The processor of claim 3, wherein the performance-guarantee instruction stream carries out a process of decoding an image, and the processor is provided in an image processing system for carrying out the process of decoding the image. ### Claim 5 (depends on 3) The processor of claim 3, wherein the performance-guarantee instruction stream carries out a process of encoding an image, and the processor is provided in an image processing system for carrying out the process of encoding the image. ### Claim 6 (depends on 1) The processor of claim 1 further comprising: an order information update unit operable to monitor, for each of the M instruction streams, the number of instructions having been output to a computing unit, and if the number of instructions having been output from an instruction stream exceeds a predetermined number, update the order information to shift down Z instruction storage areas storing Z instructions of the instruction stream in the order. ### Claim 7 (depends on 1) The processor of claim 1 further comprising: an order information update unit operable to monitor, for each of the M instruction streams, instructions having been output to a computing unit, and if a predetermined instruction among instructions of an instruction stream is output, update the order information to shift down Z instruction storage areas storing Z instructions of the instruction stream in the order. ### Claim 8 A method for use in a processor including L computing units, L being an integer of 2 or greater, the processor comprising: an instruction buffer including M×Z instruction storage areas each storing one instruction, M instruction streams being input in a state of being distinguished from each other, each of the M instruction streams including Z instructions, M being an integer of 2 or greater, Z being an integer of 2 or greater, M×Z being equal to or greater than L; and an order information holding unit holding M×Z pieces of order information that indicate an order of the M×Z instruction storage areas of the instruction buffer, the method comprising the steps of: extracting instructions from the M×Z instruction storage areas of the instruction buffer; and causing the extracting step to extract L instructions in executable state from the M×Z instruction storage areas in accordance with the order indicated by the order information held by the order information holding unit, and inputting the extracted L instructions into different ones of the L computing units.