# US 8,788,792 B2 · Apparatus for executing programs for a first computer architecture on a computer of a second architecture > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,788,792 B2 - Document ID: US8788792B2 - Status: Granted - Kind: B2 - Application number: 13/371,766 - Filed: 2012-02-13 - Published: 2012-06-07 - Granted: 2014-07-22 - Earliest claimed: 1999-01-28 - Assignees: ATI Technologies ULC - Applicants: John S. Yates, Jr.; Matthew F. Storch; Sandeep Nijhawan; Dale R. Jurich; Korbin S. Van Dyke - Inventors: John S. Yates, Jr.; Matthew F. Storch; Sandeep Nijhawan; Dale R. Jurich; Korbin S. Van Dyke - Web page: https://patentgrep.com/patent/US8788792B2 ## CPC - G06F 9/45554: {Instruction set architectures of guest OS and hypervisor or native processor differ, e.g. Bochs or VirtualPC on PowerPC MacOS} - G06F 9/30174: {for non-native instruction set, e.g. Javabyte, legacy code} - G06F 9/30189: {according to execution mode, e.g. mode flag} - G06F 9/3861: {Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A multi-instruction set architecture (ISA) computer system includes a computer program, a first processor, a second processor, a profiler, and a translator. The computer program includes instructions of a first ISA, the first ISA having a first complexity. The first processor is configured to execute instructions of the first ISA. The second processor is configured to execute instructions of a second ISA, the second ISA being different than the first ISA and having a second complexity, wherein the second complexity is less than the first complexity. The profiler is configured to select a block of the computer program for translation to instructions of the second ISA, wherein the block includes one or more instructions of the first ISA. The translator is configured to translate the block of the first ISA into instructions of the second ISA for execution by the second processor. ## Claims ### Claim 1 A multi-instruction set architecture (ISA) computer system, comprising: a computer program including instructions of a first ISA, the first ISA having a first complexity; a first processor configured to execute instructions of the first ISA; a second processor configured to execute instructions of a second ISA, the second ISA being different than the first ISA and having a second complexity, wherein the second complexity is less than the first complexity; wherein the ISA is indicated in the computer program by one bit in each page of instructions in the computer program; a profiler configured to select a block of the computer program for translation to instructions of the second ISA, wherein the block includes one or more instructions of the first ISA; and a translator configured to translate the block of the first ISA into instructions of the second ISA for execution by the second processor. ### Claim 2 (depends on 1) The multi-ISA computer system of claim 1, wherein the second processor is further configured to execute a first instruction of the second ISA in parallel with a second instruction of the second ISA. ### Claim 3 (depends on 1) The multi-ISA computer system of claim 1, wherein the profiler is further configured to select the block for translation based on the block being well-suited for parallel execution by the second processor. ### Claim 4 (depends on 3) The multi-ISA computer system of claim 3, wherein the profiler is further configured to select the block based on the block being data independent. ### Claim 5 (depends on 1) The multi-ISA computer system of claim 1, wherein the profiler is further configured to select the block for translation based on the block having a speed-optimal translation in the second ISA, whereby the block of the second ISA is executed faster by the second processor than the block of the first ISA would be executed by the first processor. ### Claim 6 (depends on 1) The multi-ISA computer system of claim 1, wherein the profiler is further configured to select the block based on predefined selection criteria. ### Claim 7 (depends on 1) The multi-ISA computer system of claim 1, wherein the translator is further configured to translate the block of the first ISA as a single unit such that instructions in the block of the first ISA may be translated into instructions of the second ISA that are reordered, pipelined, or executed in parallel. ### Claim 8 (depends on 7) The multi-ISA computer system of claim 7, wherein the translator is further configured to translate the block of the first ISA into data-independent instructions of the second ISA. ### Claim 9 (depends on 1) The multi-ISA computer system of claim 1, wherein the translator is further configured to translate the block from the first ISA to the second ISA for faster execution of the block. ### Claim 10 (depends on 1) The multi-ISA computer system of claim 1, wherein the first ISA is a complex instruction set computing (CISC) instruction set, and the second ISA is a reduced instruction set computing (RISC) instruction set. ### Claim 11 A method for executing a computer program of a first instruction set architecture (ISA) on a multi-ISA computer system, the method comprising: analyzing the computer program to identify a block of the computer program which would run faster as translated instructions of a second ISA; wherein the ISA is indicated in the computer program by one bit in each page of instructions in the computer program; selecting the block for translation to instructions of the second ISA based on the analyzing, wherein the block includes one or more instructions of the first ISA; translating the block of the first ISA into instructions of the second ISA; executing instructions of the computer program of the first ISA by a first processor not selected for translation; and executing the instructions of the second ISA by a second processor; wherein the first ISA is different than the second ISA, and wherein the first ISA has a first complexity and the second ISA has a second complexity that is less than the first complexity. ### Claim 12 (depends on 11) The method of claim 11, wherein the selecting includes selecting the block for translation based on the block being well-suited for parallel execution by the second processor. ### Claim 13 (depends on 12) The method of claim 12, wherein the selecting includes selecting the block based on the block being data independent. ### Claim 14 (depends on 11) The method of claim 11, wherein the selecting includes selecting the block for translation based on the block having a speed-optimal translation in the second ISA, whereby the block of the second ISA is executed faster by the second processor than the block of the first ISA would be executed by the first processor. ### Claim 15 (depends on 11) The method of claim 11, wherein the selecting includes selecting the block based on predefined selection criteria. ### Claim 16 (depends on 11) The method of claim 11, wherein the translating includes translating the block as a single unit such that instructions in the block of the first ISA may be translated into instructions of the second ISA that are reordered, pipelined, or executed in parallel. ### Claim 17 (depends on 16) The method of claim 16, wherein the translating includes translating the block into data-independent instructions of the second ISA. ### Claim 18 (depends on 11) The method of claim 11, wherein the translating includes translating the block from the first ISA to faster-executed instructions of the second ISA. ### Claim 19 (depends on 11) The method of claim 11, wherein the executing the instructions of the second ISA by the second processor includes executing the instructions of the second ISA in parallel by the second processor. ### Claim 20 (depends on 11) The method of claim 11, wherein the first ISA is a complex instruction set computing (CISC) instruction set, and the second ISA is a reduced instruction set computing (RISC) instruction set.