# US 8,788,782 B2 · Apparatus and method for memory management and efficient data processing

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- Number: US 8,788,782 B2
- Document ID: US8788782B2
- Status: Granted
- Kind: B2
- Application number: 12/540,756
- Filed: 2009-08-13
- Published: 2011-02-17
- Granted: 2014-07-22
- Earliest claimed: 2009-08-13
- Assignees: QUALCOMM Incorporated
- Applicants: Mathias Kohlenz; Idreas Mir; Irfan Anwar Khan; Sathyanarayan Madhusudan; Shailesh Maheshwari; Srividhya Krishnamoorthy; Sandeep Urgaonkar; Thomas Klingenbrunn; Tim Liou
- Inventors: Mathias Kohlenz; Idreas Mir; Irfan Anwar Khan; Sathyanarayan Madhusudan; Shailesh Maheshwari; Srividhya Krishnamoorthy; Sandeep Urgaonkar; Thomas Klingenbrunn; Tim Liou
- Web page: https://patentgrep.com/patent/US8788782B2

## CPC

- G06F 9/5016: {the resource being the memory}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Multiple memory pools are defined in hardware for operating on data. At least one memory pool has a lower latency that the other memory pools. Hardware components operate directly on data in the lower latency memory pool.

## Claims

### Claim 1

A data processing method, comprising:
defining a first memory pool in a first physical memory;
defining a second memory pool in a second physical memory distinct from the first physical memory, the second memory pool having a lower latency than the first memory pool; and
programming, by a processor executing a software component, a hardware component to operate on the first memory pool or operate directly on the second memory pool based on one or more predetermined criteria,
wherein defining the second memory pool comprises defining the size of the second memory pool such that a majority of data operations of the hardware component are performed using the second memory pool, and
wherein the hardware component is programmed to operate directly on the second memory pool by maintaining data in the second memory pool whenever space is available,
wherein the hardware component and the software component operate on data stored in the second memory pool when processing the data at each of a plurality of protocol layers, wherein the data is not copied to the first memory pool after processing at each of the plurality of protocol layers.

### Claim 2 (depends on 1)

The method of claim 1, wherein the one or more predetermined criteria are based on data transmission characteristics.

### Claim 3 (depends on 1)

The method of claim 1, wherein the hardware component comprises a hardware accelerator.

### Claim 4

At least one hardware processor, comprising:
a first module for defining a first memory pool in a first physical memory;
a second module for defining a second memory pool in a second physical memory distinct from the first physical memory, the second memory pool having a lower latency that the first memory pool; and
a third module for programming a hardware component to operate on the first memory pool or operate directly on the second memory pool based on one or more predetermined criteria,
wherein the second module is configured to define the size of the second memory pool such that a majority of data operations of the hardware component are preformed using the second memory pool, and
wherein the third module is configured to program the hardware component to operate on the second memory pool whenever space is available by maintaining data in the second memory pool,
wherein the hardware component and a software component executed by the hardware processor operate on data stored in the second memory pool when processing the data at each of a plurality of protocol layers, wherein the data is not copied to the first memory pool after processing at each of the plurality of protocol layers.

### Claim 5

A computer program product, comprising:
a non-transitory computer-readable medium comprising:
a first set of codes for causing a computer to define a first memory pool in a first physical memory;
a second set of codes for causing the computer to define a second memory pool in a second physical memory distinct from the first physical memory, the second memory pool having a lower latency that the first memory pool;
a third set of codes for causing the computer to program a hardware component to operate on the first memory pool or operate directly on the second memory pool based on one or more predetermined criteria,
wherein the second set of codes causes the computer to define the size of the second memory pool such that a majority of data operations of the hardware component are preformed using the second memory pool, and
wherein the third set of codes causes the computer to program the hardware component to operate on the second memory pool whenever space is available by maintaining data in the second memory pool,
wherein the hardware component and a software component executed by a hardware processor distinct from the hardware component operate on data stored in the second memory pool when processing the data at each of a plurality of protocol layers, wherein the data is not copied to the first memory pool after processing at each of the plurality of protocol layers.

### Claim 6

An apparatus, comprising:
means for defining a first memory pool in a first physical memory;
means for defining a second memory pool in a second physical memory distinct from the first physical memory, the second memory pool having a lower latency that the first memory pool; and
means for programming a hardware component to operate on the first memory pool or operate directly on the second memory pool based on one or more predetermined criteria,
wherein the means for defining the second memory pool defines the size of the second memory pool such that majority of data operations of the hardware component are preformed using the second memory pool, and
wherein the means for programming the hardware component programs the hardware component to operate on the second memory pool whenever space is available by maintaining data in the second memory pool,
wherein the hardware component and a software component executed by a hardware processor distinct from the hardware component operate on data stored in the second memory pool when processing the data at each of a plurality of protocol layers, wherein the data is not copied to the first memory pool after processing at each of the plurality of protocol layers.

### Claim 7

An data processing apparatus, comprising:
a processor;
a first memory pool in a first physical memory;
a second memory pool in a second physical memory distinct from the first physical memory, the second memory pool having a lower latency that the first memory pool; and
a hardware component operable on the first memory pool or operable directly on the second memory pool based on one or more predetermined criteria, the hardware component being controlled by the processor,
wherein the second memory pool has a capacity to accommodate a majority of data operations of the hardware component, and
wherein the hardware component is programmed to operate on the second memory pool whenever space is available by maintaining data in the second memory pool,
wherein the hardware component and a software component executed by the processor operate on data stored in the second memory pool when processing the data at each of a plurality of protocol layers, wherein the data is not copied to the first memory pool after processing at each of the plurality of protocol layers.

### Claim 8 (depends on 7)

The data processing apparatus of claim 7, wherein the one or more predetermined criteria are based on data transmission characteristics.

### Claim 9 (depends on 7)

The data processing apparatus of claim 7, wherein the hardware component comprises a hardware accelerator.