# US 8,788,775 B2 · Memory access control using redundant and non-redundant encoding > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,788,775 B2 - Document ID: US8788775B2 - Status: Granted - Kind: B2 - Application number: 13/067,812 - Filed: 2011-06-28 - Published: 2012-02-16 - Granted: 2014-07-22 - Earliest claimed: 2010-08-11 - Assignees: Arm Limited - Applicants: Richard Roy Grisenthwaite - Inventors: Richard Roy Grisenthwaite - Web page: https://patentgrep.com/patent/US8788775B2 ## CPC - G06F 12/145: {the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism} - G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields} - G06F 9/30189: {according to execution mode, e.g. mode flag} - G06F 2212/1004: Compatibility, e.g. with legacy hardware - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A data processing system 2 including processing circuitry 4 operating in either a first mode or a second mode. Page table data 30 including access control bits 40, 42, is used to control permissions for memory access to memory pages. In the first mode, the access control bits include at least one instance of a redundant encoding. In the second mode, the redundant encoding is removed to provide more efficient use of the access control bit encoding space. ## Claims ### Claim 1 Apparatus for processing data comprising: processing circuitry responsive to program instructions to perform data processing operations and configured to operate in a plurality of modes; and memory management circuitry coupled to said processing circuitry and to a memory and configured to control access permissions to data values stored within said memory in dependence upon page table data; wherein said memory has a memory address space divided in to a plurality of memory pages and said page table data comprises a plurality of access control bits for each of said plurality of memory pages defining access permissions for a respective memory page; when said processing circuitry is in a first of said plurality of modes using a predetermined number of access control bits to encode access permissions, said memory management circuitry is responsive to at least one instance of a redundant encoding in which a plurality of different combinations of said access control bits provides a same set of access permissions; and when said processing circuitry is in a second of said plurality of modes using said predetermined number of access control bits to encode access permissions, said memory management circuitry is responsive to said plurality of different combinations of access control bits to provide a plurality of different sets of access permissions in a non-redundant encoding. ### Claim 2 (depends on 1) Apparatus as claimed in claim 1, wherein said plurality of different sets of access permissions include said same set of access permissions providing a set of access control bit values that are compatible between operation in said first of said plurality of modes and said second of said plurality of modes. ### Claim 3 (depends on 1) Apparatus as claimed in claim 1, wherein in said first of said modes said access permissions must specify that data values stored within a memory page are readable in order for said data values within said memory page to be executable. ### Claim 4 (depends on 3) Apparatus as claimed in claim 3, wherein in said second of said modes said access permissions need not specify that data values stored within a memory page are readable in order for said data values within said memory page to be executable, such that said data values may not be read as data, but said data values may be executed as instructions. ### Claim 5 (depends on 1) Apparatus as claimed in claim 1, wherein said processing circuitry is configured to operate at a plurality of exception levels within each of said plurality of modes, said plurality of exception levels including a user level and a privileged level, said privileged level providing greater access to resources of said apparatus. ### Claim 6 (depends on 5) Apparatus as claimed in claim 5, wherein a first of said access control bits controls said memory management circuitry selectively to prevent execution of instructions from a corresponding memory page when said processing circuitry is at both said user level and at said privileged level when said processing circuitry is in said first of said plurality of modes. ### Claim 7 (depends on 6) Apparatus as claimed in claim 6, said first of said access control bits controls said memory management circuitry selectively to prevent execution of instructions from a corresponding memory page when said processing circuitry is at said user level but not at said privileged level when said processing circuitry is in said second of said plurality of modes. ### Claim 8 (depends on 6) Apparatus as claimed in claim 6, wherein a second of said access control bits controls said memory management circuitry selectively to prevent execution of instructions from a corresponding memory page when said processing circuitry is at said privileged level when said processing circuitry is in both said first of said plurality of modes and said second of said plurality of modes. ### Claim 9 (depends on 4) Apparatus as claimed in claim 4, wherein for at least some combinations of said access control bits for a memory page when said processing circuitry is operating at said user level, said memory management circuitry permits execution of instructions from said memory page but does not permit read access and write access to said memory page. ### Claim 10 (depends on 1) Apparatus as claimed in claim 1, wherein when said access control bits provide write access to a memory page, said memory management circuitry is responsive to an execute control override parameter to prevent execution of instructions read from said memory page irrespective of any execute permission specified by said access control bits. ### Claim 11 (depends on 1) Apparatus as claimed in claim 1, wherein when operating in said first of said plurality of modes said processing circuitry is responsive to program instructions from a first instruction set and when operating in said second of said plurality of modes said processing circuitry is responsive to program instructions from a second instruction set. ### Claim 12 Apparatus for processing data comprising: processing means for performing data processing operations in response to program instructions, said processing means being configured to operate in a plurality of modes; and memory management means coupled to said processing means and to a memory for controlling access permissions to data values stored within said memory in dependence upon page table data; wherein said memory has a memory address space divided in to a plurality of memory pages and said page table data comprises a plurality of access control bits for each of said plurality of memory pages defining access permissions for a respective memory page; when said processing means is in a first of said plurality of modes using a predetermined number of access control bits to encode access permissions, said memory management means is responsive to at least one instance of a redundant encoding in which a plurality of different combinations of said access control bits provides a same set of access permissions; and when said processing means is in a second of said plurality of modes using said predetermined number of access control bits to encode access permissions, said memory management means is responsive said plurality of different combinations of access control bits to provide a plurality of different sets of access permissions in a non-redundant encoding. ### Claim 13 A method of processing data comprising the steps of: performing data processing operations with processing circuitry in response to program instructions, said processing circuitry being configured to operate in a plurality of modes; and controlling access permissions to data values stored within said memory in dependence upon page table data; wherein said memory has a memory address space divided in to a plurality of memory pages and said page table data comprises a plurality of access control bits for each of said plurality of memory pages defining access permissions for a respective memory page; when said processing circuitry is in a first of said plurality of modes using a predetermined number of access control bits to encode access permissions, said access control bits provide to at least one instance of a redundant encoding in which a plurality of different combinations of said access control bits provides a same set of access permissions; and when said processing circuitry is in a second of said plurality of modes using said predetermined number of access control bits to encode access permissions, said plurality of different combinations of access control bits provide a plurality of different sets of access permissions in a non-redundant encoding. ### Claim 14 (depends on 13) A method as claimed in claim 13, wherein said plurality of different sets of access permissions include said same set of access permissions providing a set of access control bit values that are compatible between operation in said first of said plurality of modes and said second of said plurality of modes. ### Claim 15 (depends on 13) A method as claimed in claim 13, wherein in said first of said modes said access permissions must specify that data values stored within a memory page are readable in order for said data values within said memory page to be executable. ### Claim 16 (depends on 15) A method as claimed in claim 15, wherein in said second of said modes said access permissions need not specify that data values stored within a memory page are readable in order for said data values within said memory page to be executable, such that said data values may not be read as data, but said data values may be executed as instructions. ### Claim 17 (depends on 13) A method as claimed in claim 13, wherein said processing circuitry is configured to operate at a plurality of exception levels within each of said plurality of modes, said plurality of exception levels including a user level and a privileged level, said privileged level providing greater access to resources of an apparatus performing said method. ### Claim 18 (depends on 17) A method as claimed in claim 17, wherein a first of said access control bits controls selective prevention of execution of instructions from a corresponding memory page when said processing circuitry is at both said user level and at said privileged level when said processing circuitry is in said first of said plurality of modes. ### Claim 19 (depends on 18) A method as claimed in claim 18, said first of said access control bits controls selective prevention of execution of instructions from a corresponding memory page when said processing circuitry is at said user level but not at said privileged level when said processing circuitry is in said second of said plurality of modes. ### Claim 20 (depends on 18) A method as claimed in claim 18, wherein a second of said access control bits controls said memory management circuitry selectively to prevent execution of instructions from a corresponding memory page when said processing circuitry is at said privileged level when said processing circuitry is in both said first of said plurality of modes and said second of said plurality of modes. ### Claim 21 (depends on 16) A method as claimed in claim 16, wherein for at least some combinations of said access control bits for a memory page when said processing circuitry is operating at said user level, execution of instructions from said memory page is permitted but read access and write access to said memory page is not permitted. ### Claim 22 (depends on 13) A method as claimed in claim 13, wherein when said access control bits provide write access to a memory page, an execute control override parameter serves to control prevention of execution of instructions read from said memory page irrespective of any execute permission specified by said access control bits. ### Claim 23 (depends on 13) A method as claimed in claim 13, wherein when operating in said first of said plurality of modes said processing circuitry is responsive to program instructions from a first instruction set and when operating in said second of said plurality of modes said processing circuitry is responsive to program instructions from a second instruction set. ### Claim 24 (depends on 13) A non-transitory, computer-readable medium comprising a virtual machine, said virtual machine comprising a computer program controlling a computer to perform a method as claimed in claim 13.