# US 8,788,765 B2 · Buffer control system and method for a memory system having outstanding read and write request buffers > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,788,765 B2 - Document ID: US8788765B2 - Status: Granted - Kind: B2 - Application number: 13/960,243 - Filed: 2013-08-06 - Published: 2013-12-05 - Granted: 2014-07-22 - Earliest claimed: 2004-01-30 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Joseph Jeddeloh - Web page: https://patentgrep.com/patent/US8788765B2 ## CPC - G06F 3/0656: {Data buffering arrangements} - G06F 3/0604: {Improving or facilitating administration, e.g. storage management} - G06F 3/067: {Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]} - G06F 13/1642: {with request queuing} - G06F 13/1673: {using buffers} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A memory controller and method for managing the issuance of read and write requests to a system memory is provided. The number of outstanding read requests and write requests issued to the system memory are separately monitored and further issuance of read and write requests to the system memory is separately controlled based on the number of outstanding read and write requests, respectively. For example, the issuance of read and write requests can be managed by halting and resuming the issuance of read and write requests to the system memory to maintain the number of outstanding read requests between first and second read thresholds and to maintain the number of outstanding write requests between first and second write thresholds, respectively. ## Claims ### Claim 1 A memory controller for use with a system memory, the memory controller comprising: a flow control unit comprising: a first buffer control circuit configured to determine a number of outstanding memory requests of a first kind issued to the system memory; and a second buffer control circuit configured to determine a number of outstanding memory requests of a second kind issued to the system memory, wherein the flow control unit is configured to provide a flow control signal to control further issuance of memory requests of the first and second kinds to the system memory based on the numbers of outstanding memory requests of the first and second kinds, respectively, including enabling issuance of additional memory requests of the first kind to the system memory when the number of outstanding memory requests of the first kind is within a range and halting issuance of additional memory requests of the first kind when the number of outstanding memory requests of the first kind is outside of the range. ### Claim 2 (depends on 1) The memory controller of claim 1, wherein each of the first buffer control circuit and the second buffer control circuit comprises a counter. ### Claim 3 (depends on 1) The memory controller of claim 1, wherein the outstanding memory requests of the first kind comprise read requests. ### Claim 4 (depends on 1) The memory controller of claim 1, wherein the range is a first range and wherein the flow control unit is further configured to enable issuance of additional memory requests of the second kind to the system memory when the number of outstanding memory requests of the second kind is within a second range, and to halt issuance of additional memory requests of the second kind when the number of outstanding memory requests of the second kind is outside of the second range. ### Claim 5 (depends on 1) The memory controller of claim 1, wherein the first buffer control circuit is included in a plurality of first buffer control circuits, each of the first buffer control circuits corresponding to a respective buffer of the system memory. ### Claim 6 (depends on 1) The memory controller of claim 1, wherein the flow control unit is further configured to determine the number of outstanding memory requests of the first and second kinds based, at least in part, on a plurality of request ID signals and a plurality of response signals. ### Claim 7 (depends on 1) The memory controller of claim 1, wherein the range is fixed. ### Claim 8 An apparatus, comprising: a controller configured to determine a number of outstanding memory requests of a first type issued to a memory and determine a number of outstanding memory requests of a second type issued to the memory, the controller further configured to control issuance of memory requests of the first type to the memory based, at least in part, on the number of outstanding memory requests of the first type and to control issuance of memory requests of the second type to the memory based, at least in part, on the number of outstanding memory requests of the second type. ### Claim 9 (depends on 8) The apparatus of claim 8, wherein the controller is further configured to selectively provide a first flow control signal to control issuance of memory requests of the first type to the memory and to selectively provide a second flow control signal to control issuance of memory requests of the second type to the memory. ### Claim 10 (depends on 8) The apparatus of claim 8, wherein the controller is further configured to maintain the number of outstanding memory requests of the first type above a first threshold and to maintain the number of outstanding memory requests of the second type above a second threshold. ### Claim 11 (depends on 10) The apparatus of claim 10, wherein the first threshold is different than the second threshold. ### Claim 12 (depends on 10) The apparatus of claim 10, wherein at least one of the first threshold or the second threshold is programmable. ### Claim 13 (depends on 8) The apparatus of claim of claim 8, wherein the controller comprises: a first buffer control circuit configured to monitor the number of outstanding memory requests of the first type; and a second buffer control circuit configured to monitor the number of outstanding memory requests of the second type. ### Claim 14 An apparatus, comprising: a request queue configured to receive memory requests of a first type and memory requests of a second type, the request queue configured to selectively provide the memory requests of the first type according to a first flow control signal and to selectively provide the memory requests of the second type according to a second flow control signal; and a flow control unit configured to determine a number of outstanding memory requests of the first type and to determine a number of outstanding memory requests of the second type, the flow control unit further configured to provide the first flow control signal and the second flow control signal, the first flow control signal based, at least in part, on the number of outstanding memory requests of the first type and the second flow control signal based, at least in part, on the number of outstanding memory requests of the second type. ### Claim 15 (depends on 14) The apparatus of claim 14, wherein the memory requests of a first type comprise read requests and the memory requests of a second type comprise write requests. ### Claim 16 (depends on 14) The apparatus of claim 14, wherein the flow control unit is configured to determine a number of outstanding memory requests of the first type based, at least in part, on a plurality of request ID signals and a plurality of response signals. ### Claim 17 (depends on 14) The apparatus of claim 14, wherein the flow control unit is configured to provide the first flow control signal to halt issuance of the memory requests of the first type responsive, at least in part, to the number of outstanding memory requests of the first type exceeding a first threshold and to provide the second flow control signal to halt issuance of the memory requests of the second type responsive, at least in part, to the number of outstanding memory requests of the second type exceeding a second threshold. ### Claim 18 (depends on 17) The apparatus of claim 17, wherein the first and second thresholds are different. ### Claim 19 (depends on 14) The apparatus of claim 14, wherein the flow control unit comprises: a first buffer control circuit configured to monitor the number of outstanding memory requests of a first type; and a second buffer control circuit configured to monitor the number of outstanding memory requests of a second kind. ### Claim 20 (depends on 14) The apparatus of claim 14, wherein a flow control unit is configured to determine a number of outstanding memory requests of the first type by monitoring a servicing of at least one memory request.