# US 8,788,759 B2 · Double-buffered data storage to reduce prefetch generation stalls > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,788,759 B2 - Document ID: US8788759B2 - Status: Granted - Kind: B2 - Application number: 13/223,237 - Filed: 2011-08-31 - Published: 2012-03-22 - Granted: 2014-07-22 - Earliest claimed: 2010-09-21 - Assignees: Texas Instruments Incorporated - Applicants: Matthew D Pierson; Joseph R M Zbiciak - Inventors: Matthew D Pierson; Joseph R M Zbiciak - Web page: https://patentgrep.com/patent/US8788759B2 ## CPC - G06F 12/0897: with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811) - G06F 12/0811: with multilevel cache hierarchies - G06F 12/0862: with prefetch - G06F 9/3802: {Instruction prefetching} - G06F 9/3806: {using address prediction, e.g. return stack, branch history buffer} - G06F 9/3844: {using dynamic branch prediction, e.g. using branch history tables} - G06F 12/0886: Variable-length word access - G06F 2212/602: Details relating to cache prefetching - G06F 2212/6022: Using a prefetch buffer or dedicated prefetch cache - G06F 2212/6028: Prefetching based on hints or prefetch instructions - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract A prefetch unit includes a program prefetch address generator that receives memory read requests and in response to addresses associated with the memory read request generates prefetch addresses and stores the prefetch addresses in slots of the prefetch unit buffer. Each slot includes a buffer for storing a prefetch address, two data buffers for storing data that is prefetched using the prefetch address of the slot, and a data buffer selector for alternating the functionality of the two data buffers. A first buffer is used to hold data that is returned in response to a received memory request, and a second buffer is used to hold data from a subsequent prefetch operation having a subsequent prefetch address, such that the data in the first buffer is not overwritten even when the data in the first buffer is still in the process of being read out. ## Claims ### Claim 1 A method for generating memory prefetches in caching systems, comprising: generating prefetch addresses in response to addresses associated with memory read requests; storing the prefetch addresses in slots of a prefetch buffer, wherein each slot includes a buffer for storing a prefetch address, a first data buffer and second data buffer for storing data that is prefetched using the prefetch address stored in the slot, and a data buffer selector for alternating a designation of the first and second buffers; allocating a slot associated with a next predicted address in accordance with an order in which a prefetch FIFO counter is modified to cycle through the slots of an array of slots before wrapping around to a first slot of the array for storing portions of predicted addresses; in the allocated slot, reading data from the first data buffer, and storing subsequent data from a subsequent prefetch operation having a subsequent prefetch address in the second data buffer before completing the operation of reading the data in the first buffer; and alternating the designation of the first and second buffers by modifying the state of the data buffer selector after the subsequent data has been stored in the second data buffer. ### Claim 2 (depends on 1) The method of claim 1, comprising storing metadata associated with a status of each slot within each slot. ### Claim 3 (depends on 2) The method of claim 2, wherein the stored metadata associated with the status of each slot includes a data pending indicator and a data valid indicator. ### Claim 4 (depends on 1) The method of claim 1, comprising maintaining an array of request slots for received memory requests and processing the requests according to a First In, First Out (FIFO) policy. ### Claim 5 (depends on 4) The method of claim 4, wherein each request slot of the array of request slots for the received memory requests includes a buffer for the address and a prefetch buffer slot number allocated for the address. ### Claim 6 (depends on 4) The method of claim 4, wherein the prefetch buffer slot number associated with a request slot that is currently being processed is used to enable the reading data from the first data buffer. ### Claim 7 (depends on 1) The method of claim 1, wherein a prefetch buffer slot number associated with the slot to be processed after a currently processed request slot is used to provision the reading data from the first data buffer of the slot pointed to by the prefetch buffer slot number associated with the slot to be processed after the currently processed request slot. ### Claim 8 (depends on 1) The method of claim 1, wherein the memory read request associated with the allocated slot is associated with a program stream issued by a processor. ### Claim 9 (depends on 1) The method of claim 1, wherein the prefetched data is retrieved from a main memory. ### Claim 10 (depends on 1) The method of claim 1, wherein the storing subsequent data from a subsequent prefetch operation having a subsequent prefetch address in the second data buffer is performed while the data in the first buffer is in a return-wait situation. ### Claim 11 (depends on 1) The method of claim 1, comprising storing metadata associated with the subsequent prefetch operation in a buffer associated with the allocated slot. ### Claim 12 A digital system, comprising: a memory including local memory and a lower-level hierarchical memory for storing and retrieving data; a prefetch unit that includes a prefetch address generator that is arranged to generate prefetch addresses in response to addresses associated with memory read requests, a prefetch buffer that is arranged to store the prefetch addresses in slots of the prefetch buffer, wherein each slot includes a buffer for storing a prefetch address, a first data buffer and second data buffer for storing data that is prefetched using the prefetch address stored in the same slot, and a data buffer selector for alternating designation of the first and second data buffers, a data buffer selector that is arranged to alternate the designation of the first and second data buffers in a selected slot in response to a return-wait situation wherein subsequent data from a subsequent prefetch operation having a subsequent prefetch address in the second data buffer is to be stored in a second data buffer before completing the operation of reading the data in the first data buffer and a prefetch FIFO counter that is modified to cycle through the slots of an array of slots to select the selected slot before wrapping around to a first slot of the array for storing portions of predicted addresses. ### Claim 13 (depends on 12) The system of claim 12, wherein the prefetch unit includes an array of request slots that is arranged to maintain received memory requests and process the received memory requests according to a First In, First Out (FIFO) policy, wherein each request slot of the array of request slots for the received memory requests includes a buffer for the address and a prefetch buffer slot number allocated for the address. ### Claim 14 (depends on 13) The system of claim 13, wherein the prefetch buffer slot number associated with a request slot that is currently being processed is used to enable the reading data from the first data buffer. ### Claim 15 (depends on 14) The system of claim 14, wherein the prefetch buffer slot number associated with the slot to be processed after the currently processed request slot is used to provision the reading data from the first data buffer of the slot pointed to by the prefetch buffer slot number associated with the slot to be processed after the currently processed request slot.