# US 8,788,748 B2 · Implementing memory interface with configurable bandwidth

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- Number: US 8,788,748 B2
- Document ID: US8788748B2
- Status: Granted
- Kind: B2
- Application number: 13/427,078
- Filed: 2012-03-22
- Published: 2013-09-26
- Granted: 2014-07-22
- Earliest claimed: 2012-03-22
- Assignees: International Business Machines Corporation
- Applicants: Gerald K. Bartley; John M. Borkenhagen; Philip R. Germann
- Inventors: Gerald K. Bartley; John M. Borkenhagen; Philip R. Germann
- Web page: https://patentgrep.com/patent/US8788748B2

## CPC

- G11C 5/02: Disposition of storage elements, e.g. in the form of a matrix array
- G06F 13/1684: {using multiple buses}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A method and system are provided for implementing enhanced memory performance management with configurable bandwidth versus power usage in a chip stack of memory chips. A chip stack of memory chips is connected in a predefined density to allow a predefined high bandwidth connection between each chip in the stack, such as with through silicon via (TSV) interconnections. Large-bandwidth data transfers are enabled from the memory chip stack by trading off increased power usage for memory performance on a temporary basis.

## Claims

### Claim 1

A method for implementing enhanced memory performance management comprising:
providing at least one memory chip stack having a predefined connection density to enable a predefined high bandwidth connection between each chip in said memory chip stack; and
providing said at least one memory chip stack with a memory controller and a plurality of chip rank levels in said memory chip stack including at least a chip rank level one adjacent said controller; a chip rank level two above said chip rank level one; and a chip level three above said chip rank level two;
providing a normal bandwidth configuration for said at least one memory chip stack with said chip rank level one with a first bandwidth for data; said chip rank level two with a second bandwidth for data and said chip rank level three with a third bandwidth for data; said first bandwidth greater than both said second bandwidth and said third bandwidth;
selectively enabling a high bandwidth data transfer from said memory chip stack on a temporary basis; said high bandwidth data transfer including an equal bandwidth for said first bandwidth, said second bandwidth and said third bandwidth.

### Claim 2 (depends on 1)

The method as recited in claim 1 wherein providing at least one memory chip stack having a predefined connection density includes connecting said memory chip stack in a predefined density with through silicon via (TSV) interconnections.

### Claim 3 (depends on 1)

The method as recited in claim 1 wherein selectively enabling a high bandwidth data transfer from said memory chip stack on a temporary basis includes providing said memory controller coupled to said at least one memory chip stack, said controller using said bandwidth data transfer with said equal bandwidth for said first bandwidth, said second bandwidth and said third bandwidth from said memory chip stack.

### Claim 4 (depends on 3)

The method as recited in claim 3 wherein said memory controller selectively enables said high bandwidth data transfer from said memory chip stack on said temporary basis.

### Claim 5 (depends on 3)

The method as recited in claim 3 wherein said memory controller selectively requests data at a higher speed than a normal data read speed for the high bandwidth data transfers.

### Claim 6 (depends on 1)

The method as recited in claim 1 wherein providing said at least one memory chip stack having a predefined connection density includes providing said at least one memory chip stack of dynamic random access memory (DRAM) chips.

### Claim 7 (depends on 1)

The method as recited in claim 1 wherein selectively enabling a high bandwidth data transfer from said memory chip stack on a temporary basis includes receiving a request for a large direct memory access (DMA).

### Claim 8 (depends on 1)

The method as recited in claim 1 wherein providing said at least one memory chip stack having a predefined connection density includes providing a silicon carrier including said memory controller and providing said memory chip stack of a plurality of dynamic random access memory (DRAM) chips.

### Claim 9 (depends on 8)

The method as recited in claim 8 includes providing said silicon carrier with first level custom DRAM chips and said controller.

### Claim 10

A system for implementing memory performance management in a computer system comprising:
a memory including at least one memory chip stack having a predefined connection density to enable a predefined high bandwidth connection between each chip in said memory chip stack;
a memory controller coupled to said at least one memory chip stack; and said memory chip stack including a plurality of chip rank levels with a chip rank level one adjacent said controller; a chip rank level two above said chip rank level one; and a chip level three above said chip rank level two;
a data transfer bandwidth control;
said memory controller, responsive to said data transfer bandwidth control, providing a normal bandwidth configuration for said at least one memory chip stack including said chip rank level one with a first bandwidth for data; said chip rank level two with a second bandwidth for data and said chip rank level three with a third bandwidth for data; said first bandwidth greater than both said second bandwidth and said third bandwidth;
said memory controller, responsive to said data transfer bandwidth control, selectively enabling a high bandwidth data transfer from said memory chip stack on a temporary basis; said high bandwidth data transfer including an equal bandwidth for said first bandwidth, said second bandwidth and said third bandwidth.

### Claim 11 (depends on 10)

The system as recited in claim 10 includes through silicon via (TSV) interconnections between each chip in said memory chip stack.

### Claim 12 (depends on 10)

The system as recited in claim 10 includes said controller using said first bandwidth for said high bandwidth data transfer from said memory chip stack.

### Claim 13 (depends on 10)

The system as recited in claim 10 wherein said at least one memory chip stack includes a plurality of dynamic random access memory (DRAM) chips.

### Claim 14 (depends on 10)

The system as recited in claim 10 includes a silicon carrier supporting said at least one memory chip stack and includes said memory controller.

### Claim 15 (depends on 14)

The system as recited in claim 14 wherein said silicon carrier includes first level custom DRAM chips of said at least one memory chip stack.

### Claim 16 (depends on 10)

The system as recited in claim 10 wherein said data transfer bandwidth control includes a data transfer bandwidth control computer program product tangibly embodied on a non-transitory computer readable storage medium.

### Claim 17 (depends on 10)

The system as recited in claim 10 wherein said at least one memory chip stack includes a plurality of dynamic random access memory (DRAM) chips logically arranged in three levels.