# US 8,788,744 B2 · Memory control device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,788,744 B2 - Document ID: US8788744B2 - Status: Granted - Kind: B2 - Application number: 13/453,169 - Filed: 2012-04-23 - Published: 2013-04-18 - Granted: 2014-07-22 - Earliest claimed: 2011-10-13 - Assignees: Nuvoton Technology Corporation - Applicants: Shuang-Yi Tan; Yueh-Yao Nain; Der-Ing Hsu - Inventors: Shuang-Yi Tan; Yueh-Yao Nain; Der-Ing Hsu - Web page: https://patentgrep.com/patent/US8788744B2 ## CPC - G06F 12/0238: {Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory} - G06F 13/1684: {using multiple buses} - G06F 13/4022: {using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A memory control device for controlling a primary controller and a secondary controller to access a flash memory is provided. A bus switch is coupled to the primary controller, the secondary controller and the flash memory via a first, second and third serial peripheral interface (SPI) buses, respectively. A selecting unit selectively couples the third SPI bus to one of the first and second buses. When the bus switch receives an access request from the primary controller via the first SPI bus, the selecting unit couples the third SPI bus to the first SPI bus, so as to transmit a chip select signal, a clock signal and a master output slave input (MOSI) signal from the primary controller to the flash memory for accessing the flash memory. The first access request is provided by the first chip select signal. ## Claims ### Claim 1 A memory control device for controlling a primary controller and a secondary controller to access a flash memory, comprising: a bus switch coupled to the primary controller, the secondary controller and the flash memory via a first, second and third serial peripheral interface (SPI) buses, respectively, comprising: a selecting unit, selectively coupling the third SPI bus to one of the first and second buses, wherein when the bus switch receives a first access request from the primary controller via the first SPI bus, the selecting unit couples the third SPI bus to the first SPI bus, so as to transmit a first chip select signal, a first clock signal and a first master output slave input (MOSI) signal from the primary controller to the flash memory for accessing the flash memory, wherein the first access request is provided by the first chip select signal. ### Claim 2 (depends on 1) The memory control device as claimed in claim 1, wherein when the first chip select signal indicates that the first access request of the primary controller has been completed and the bus switch receives a second access request from the secondary controller via the second SPI bus, the selecting unit couples the third SPI bus to the second SPI bus, so as to transmit a second chip select signal, a second clock signal and a second MOSI signal from the secondary controller to the flash memory for accessing the flash memory. ### Claim 3 (depends on 1) The memory control device as claimed in claim 1, wherein a first master input slave output (MISO) signal of the primary controller and a second MISO signal of the secondary controller are directly provided by an output signal of the flash memory without passing through the first, second and third SPI buses. ### Claim 4 (depends on 1) The memory control device as claimed in claim 1, wherein the first MOSI signal comprises command information and address information, and the bus switch further comprises: a first processing unit coupled between the first SPI bus and the selecting unit, delaying the first chip select signal, the first clock signal and the first MOSI signal and adjusting the timing of the first MOSI signal and the first clock signal corresponding to the command information when the first access request from the primary controller is received via the first SPI bus, such that timing of the first MOSI signal and the first clock signal corresponding to the address information from the first processing unit to the flash memory synchronize to the timing of the first MOSI signal and the first clock signal corresponding to the address information from the primary controller to the first processing unit. ### Claim 5 (depends on 4) The memory control device as claimed in claim 4, further comprising: a second processing unit coupled between the first processing unit and the selecting unit, adjusting a duty cycle of the first clock signal to be transmitted to the selecting unit. ### Claim 6 (depends on 1) The memory control device as claimed in claim 1, wherein when the bus switch receives the first access request from the primary controller via the first SPI bus, the bus switch further sends a stop signal to the secondary controller, so as to notify the secondary controller to stop accessing the flash memory. ### Claim 7 (depends on 1) The memory control device as claimed in claim 1, further comprising: a bus share regulation unit, determining whether the secondary controller is waiting to access the flash memory and counting a wait time when the flash memory is accessed by the primary controller; and an interrupt unit, sending an interrupt request to the primary controller when the wait time exceeds a specific time, wherein the primary controller stops accessing the flash memory in response to the interrupt request. ### Claim 8 (depends on 7) The memory control device as claimed in claim 7, wherein when the first chip select signal indicates that the primary controller has stopped accessing the flash memory, the selecting unit of the bus switch couples the third SPI bus to the second SPI bus, so as to transmit a second chip select signal, a second clock signal and a second MOSI signal from the secondary controller to the flash memory for accessing the flash memory. ### Claim 9 (depends on 8) The memory control device as claimed in claim 8, wherein when the selecting unit couples the third SPI bus to the second SPI bus, the bus share regulation unit sets the counted wait time as an access time, and the interrupt unit stops sending the interrupt request to the primary controller when a time that the secondary controller accesses the flash memory, reaches the access time. ### Claim 10 (depends on 1) The memory control device as claimed in claim 1, wherein the primary controller is implemented in a chipset. ### Claim 11 (depends on 1) The memory control device as claimed in claim 1, wherein the memory control device and the primary controller are integrated into a chip of a chipset. ### Claim 12 (depends on 1) The memory control device as claimed in claim 1, wherein the memory control device and the secondary controller are implemented in a super input/output integrated circuit. ### Claim 13 (depends on 1) The memory control device as claimed in claim 1, wherein the memory control device and the flash memory are integrated into a chip. ### Claim 14 A memory control device for controlling a primary controller and a secondary controller to access a flash memory, comprising: a bus switch coupled to the primary controller, the secondary controller and the flash memory via a first, second and third serial peripheral interface (SPI) buses, respectively, selectively coupling the third SPI bus to one of the first and second buses, wherein the primary controller accesses the flash memory when the third SPI bus is coupled to the first SPI bus; a bus share regulation unit, determining whether the secondary controller is waiting to access the flash memory and counting a wait time when the flash memory is accessed by the primary controller; and an interrupt unit, sending an interrupt request to the primary controller when the wait time exceeds a specific time; wherein the primary controller stops accessing the flash memory in response to the interrupt request. ### Claim 15 (depends on 14) The memory control device as claimed in claim 14, wherein when the primary controller has stopped accessing the flash memory, the bus switch couples the third SPI bus to the second SPI bus, such that the secondary controller accesses the flash memory. ### Claim 16 (depends on 15) The memory control device as claimed in claim 15, wherein when the bus switch couples the third SPI bus to the second SPI bus, the bus share regulation unit sets the counted wait time as an access time, and the interrupt unit stops sending the interrupt request to the primary controller when a time that the secondary controller accesses the flash memory, reaches the access time. ### Claim 17 (depends on 14) The memory control device as claimed in claim 14, wherein a first master input slave output (MISO) signal of the primary controller and a second MISO signal of the secondary controller are directly provided by an output signal of the flash memory without passing through the first, second and third SPI buses. ### Claim 18 (depends on 14) The memory control device as claimed in claim 14, wherein the primary controller is implemented in a chipset. ### Claim 19 (depends on 14) The memory control device as claimed in claim 14, wherein the memory control device and the secondary controller are implemented in a super input/output integrated circuit. ### Claim 20 (depends on 14) The memory control device as claimed in claim 14, wherein the memory control device and the primary controller are integrated into a chip of a chipset.