# US 8,788,738 B2 · Semiconductor device and method of manufacturing the same

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- Number: US 8,788,738 B2
- Document ID: US8788738B2
- Status: Granted
- Kind: B2
- Application number: 13/311,392
- Filed: 2011-12-05
- Published: 2012-06-14
- Granted: 2014-07-22
- Earliest claimed: 2010-12-08
- Applicants: Yoshiro Riho
- Inventors: Yoshiro Riho
- Web page: https://patentgrep.com/patent/US8788738B2

## CPC

- G11C 7/10: Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C 5/02: Disposition of storage elements, e.g. in the form of a matrix array
- G11C 7/20: Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
- G11C 8/12: Group selection circuits, e.g. for memory block selection, chip selection, array selection
- G11C 8/18: Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 90/00: Package configurations
- G11C 29/023: {in clock generator or timing circuitry}
- G11C 29/028: {with adaption or trimming of parameters}
- H10W 72/221: {Structures or relative sizes}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/245: {of outermost layers of multilayered bumps, e.g. bump coating being only on a part of a bump core}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/922: {Bond pads being integral with underlying chip-level interconnections}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9232: {with additional elements interposed between layers}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Disclosed herein is a device that includes a first terminal operatively supplied with a pulse signal, a second terminal, a set of third terminals operatively supplied with identification information, a storage unit configured to store the identification information in response to the pulse signal, and a control unit configured to electrically disconnect the first terminal from the second terminal until the storage unit stores the identification information and electrically connect the first terminal to the second terminal after the storage unit has stored the identification information. This device may be used as each of semiconductor chips that are stacked with each other.

## Claims

### Claim 1

A device comprising:
a first terminal operatively supplied with a pulse signal;
a second terminal;
a set of third terminals operatively supplied with identification information;
a storage unit configured to store the identification information in response to the pulse signal; and
a control unit configured to electrically disconnect the first terminal from the second terminal until the storage unit stores the identification information and electrically connect the first terminal to the second terminal after the storage unit has stored the identification information.

### Claim 2 (depends on 1)

The device as claimed in claim 1, wherein the control unit includes a control circuit and a first switch coupled between the first and second terminals, the control circuit being configured to turn the first switch ON after the storage unit has stored the identification information.

### Claim 3 (depends on 2)

The device as claimed in claim 2, wherein the control unit includes a second switch coupled between the set of third terminals and the storage unit, the control circuit turns the second switch OFF after the storage unit has stored the identification information.

### Claim 4 (depends on 1)

The device as claimed in claim 1, wherein the set of third terminals is supplied with the identification information in an identification information setting mode, and the device further comprises a set of fourth terminals that cooperates with the set of third terminals to serve as data terminals in a data transfer mode.

### Claim 5 (depends on 1)

The device as claimed in claim 1, further comprising a plurality of semiconductor chips, each of the semiconductor chips comprising the first terminal, the second terminal, the set of third terminals, the storage unit and the control unit, the semiconductor chips being arranged such that the second terminal of each of the semiconductor chips is connected to the first terminal of a different one of the semiconductor chips and the set of third terminals of the semiconductor chips are connected in common to each other.

### Claim 6 (depends on 5)

The device as claimed in claim 5, wherein the control unit of each of the semiconductor chips includes a control circuit and a first switch coupled between the first and second terminals, the control circuit being configured to turn the first switch ON after the storage unit has stored the identification information.

### Claim 7 (depends on 6)

The device as claimed in claim 6, wherein the control unit of each of the semiconductor chips includes a second switch coupled between the set of third terminals and the storage unit, the control circuit turns the second switch OFF after the storage unit has stored the identification information.

### Claim 8 (depends on 1)

The device as claimed in claim 1, wherein the identification information comprises a unique identification for a semiconductor chip comprising the storage unit.

### Claim 9 (depends on 1)

The device as claimed in claim 1, wherein the identification information comprises a unique identification for a semiconductor chip corresponding to the storage unit.

### Claim 10 (depends on 1)

The device as claimed in claim 1, wherein the identification information comprises unique identification information assignable to any one of a plurality of semiconductor chips by changing an identification signal stored in the storage unit in one of the plurality of semiconductor chips so as to indicate the unique identification information in synchronism with sequential transmission of a clock signal to the plurality of semiconductor chips.