# US 8,788,732 B2 · Messaging network for processing data using multiple processor cores > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,788,732 B2 - Document ID: US8788732B2 - Status: Granted - Kind: B2 - Application number: 13/972,797 - Filed: 2013-08-21 - Published: 2013-12-19 - Granted: 2014-07-22 - Earliest claimed: 2002-10-08 - Assignees: NetLogic Microsystems, Inc. - Applicants: NetLogic Microsystems, Inc. - Inventors: Julianne J. Zhu; David T. Hass - Web page: https://patentgrep.com/patent/US8788732B2 ## CPC - G06F 13/4286: {using a handshaking protocol, e.g. RS232C link} - G06F 9/3851: {from multiple instruction streams, e.g. multistreaming} - G06F 9/3854: {Instruction completion, e.g. retiring, committing or graduating} - G06F 9/3867: {using instruction pipelines} - H04L 49/109: Integrated on microchip, e.g. switch-on-chip - G06F 12/0813: with a network or matrix configuration - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. The data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. In one aspect of an embodiment of the invention, the messaging network connects to a high-bandwidth star-topology serial bus such as a PCI express (PCIe) interface capable of supporting multiple high-bandwidth PCIe lanes. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner. ## Claims ### Claim 1 A processor, comprising: at least two processor cores; at least two communication ports; and a messaging network configured to: receive, from a first communication port from among the at least two communication ports, at least two packets of packet data for respective processing by the at least two processor cores, transmit, to the at least two processor cores, the at least two packets of packet data for the respective processing, receive, from the at least two processor cores, at least two processed packets of packet data, and transmit the at least two processed packets of packet data to a second communication port from among the at least two communication ports. ### Claim 2 (depends on 1) The processor of claim 1, wherein the respective processing includes processing of the at least two packets of packet data by the at least two processor cores based on information included in headers of the at least two packets of packet data. ### Claim 3 (depends on 1) The processor of claim 1, wherein the respective processing includes processing of the at least two packets of packet data by the at least two processor cores based on payload information included in the at least two packets of packet data. ### Claim 4 (depends on 1) The processor of claim 1, wherein the messaging network is configured to receive the at least two packets of packet data in an order that is based on a current number of credits associated with the at least two processor cores. ### Claim 5 (depends on 4) The processor of claim 4, wherein the current number of credits associated with each of the at least two processor cores is based on a processing speed associated with the at least two processor cores. ### Claim 6 (depends on 5) The processor of claim 5, wherein the messaging network is configured to transmit a packet, from among the at least two packets of packet data, to a processor core other than the at least two processor cores when a delay in processing of the packet data is determined to be greater than a predetermined threshold. ### Claim 7 (depends on 4) The processor of claim 4, wherein the current number of credits associated with the at least two processor cores is based on a delay in processing of the packet data by the at least two processor cores. ### Claim 8 (depends on 1) The processor of claim 1, wherein the at least two packets of packet data are assigned at least two sequence numbers which are forwarded to the at least two processor cores and included in the at least two processed packets of packet data to allow the at least two processed packets of packet data to be output based on the sequence number assigned to the at least two packets of packet data. ### Claim 9 (depends on 1) The processor of claim 1, wherein at least one of the at least two processor cores includes a data cache and an instruction cache, and the messaging network is disposed between the instruction cache of the at least one of the at least two processor cores and at least one of the at least two communication ports. ### Claim 10 (depends on 9) The processor of claim 9, further comprising: a data switch arrangement coupled to the data cache of the at least one of the at least two processor cores, the data switch arrangement being configured to transfer memory related information. ### Claim 11 A method, comprising: receiving, at a messaging network from a first communication port from among at least two communication ports, at least two packets of packet data for respective processing by the at least two processor cores, the messaging network being associated with the at least two processor cores and the at least two communication ports; transmitting, from the messaging network to the at least two processor cores, the at least two packets of packet data for the respective processing, receiving, at the messaging network from the at least two processor cores, at least two processed packets of packet data, and transmitting, from the messaging network to a second communication port from among the at least two communication ports, the at least two processed packets of packet data. ### Claim 12 (depends on 11) The method of claim 11, wherein the respective processing includes processing of the at least two packets of packet data by the at least two processor cores based on information included in headers of the at least two packets of packet data. ### Claim 13 (depends on 11) The method of claim 11, wherein the respective processing includes processing of the at least two packets of packet data by the at least two processor cores based on payload information included in the at least two packets of packet data. ### Claim 14 (depends on 11) The method of claim 11, wherein the receiving the at least two packets of packet data includes receiving the at least two packets of packet data in an order that is based on a current number of credits associated with the at least two processor cores. ### Claim 15 (depends on 14) The method of claim 14, wherein the current number of credits associated with each of the at least two processor cores is based on a processing speed of packet data by the at least two processor cores. ### Claim 16 (depends on 14) The method of claim 14, wherein the current number of credits associated with the at least two processor cores is based on a delay in processing of the packet data by the at least two processor cores. ### Claim 17 (depends on 16) The method of claim 16, wherein the transmitting the at least two packets of packet data for respective processing includes transmitting a packet, from among the at least two packets of packet data, to a processor core other than the at least two processor cores when the delay in processing of the packet data is determined to be greater than a predetermined threshold. ### Claim 18 (depends on 11) The method of claim 11, further comprising: assigning at least two sequence numbers to the at least two packets of packet data; forwarding the at least two sequence numbers to the at least two processor cores; including the at least two sequence numbers in the at least two processed packets of packet data, and outputting the at least two processed packets of packet data based on the sequence number assigned to each of the at least two packets of packet data. ### Claim 19 A processor, comprising: at least two processor cores, the at least two processor cores including at least two data caches and at least two instruction caches; a data switch arrangement coupled to the at least two data caches of the at least two processor cores, the data switch arrangement being configured to transfer information among the at least two processor cores; and a messaging network configured to: receive, from a first communication port, at least two packets of packet data for respective processing by the at least two processor cores, transmit, to the at least two processor cores, the at least two packets of packet data for the respective processing, receive, from the at least two processor cores, at least two processed packets of packet data, and transmit the at least two processed packets of packet data to a second communication port. ### Claim 20 (depends on 19) The processor of claim 19, wherein each of the at least two packets of packet data is assigned a sequence number which is forwarded to the at least two processor cores and is included in the at least two processed packets of packet data to allow the at least two processed packets of packet data to be output based on the sequence number assigned to each of the at least two packets of packet data.