# US 8,787,514 B2 · Apparatus and method for generating pseudo noise code

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- Number: US 8,787,514 B2
- Document ID: US8787514B2
- Status: Granted
- Kind: B2
- Application number: 13/003,374
- Filed: 2008-12-31
- Published: 2011-05-26
- Granted: 2014-07-22
- Earliest claimed: 2008-08-22
- Assignees: Electronics and Telecommunications Research Institute
- Applicants: Seung Il Myong; Jong Sub Cha; Sang Hyun Mo; Jae Heum Lee; Heyung Sub Lee; Jong Suk Chae
- Inventors: Seung Il Myong; Jong Sub Cha; Sang Hyun Mo; Jae Heum Lee; Heyung Sub Lee; Jong Suk Chae
- Web page: https://patentgrep.com/patent/US8787514B2

## CPC

- H04J 13/10: Code generation
- H04B 1/707: using direct sequence modulation
- H04J 13/0022: {PN, e.g. Kronecker}
- H04J: MULTIPLEX COMMUNICATION (transmission in general H04B; peculiar to transmission of digital information H04L5/00; systems for the simultaneous or sequential transmission of more than one television signal H04N7/08; in exchanges H04Q11/00; stereophonic systems H04S)
- H04B: TRANSMISSION

## Abstract

An apparatus and method of generating a pseudo noise (PN) code is provided. The apparatus for generating the PN code includes: a memory device unit including a plurality of memory devices; an exclusive-OR (XOR) operation unit receiving output values of at least two memory devices among output values of the plurality of memory devices to output an XOR operation value with respect to the received output values; and a PN code generation unit generating the PN code based on an output value of the XOR operation unit.

## Claims

### Claim 1

An apparatus for generating a pseudo noise (PN) code, the apparatus comprising:
a memory device unit including a plurality of memory devices;
an exclusive-OR (XOR) operation unit receiving output values of at least two memory devices among output values of the plurality of memory devices to output an XOR operation value with respect to the received output values; and
a PN code generation unit generating the PN code based on an output value of the XOR operation unit,
wherein:
the plurality of memory devices is cascaded, and
the apparatus further comprises:
an initial value storage unit storing an initial value of each of the memory devices; and
an AND operation unit outputting an AND operation value with respect to the initial value of each of the memory devices and an output value of a memory device that is positioned in a final end among the plurality of cascaded memory devices, and
a memory device that is positioned in a front end among the plurality of cascaded memory devices receives an output value of the AND operation unit with respect to the initial value of the memory device of the front end.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein each of memory devices excluding the memory device of the front end receives an XOR operation value with respect to an output value of the AND operation unit associated with the initial value of each of the memory devices and an output value of a memory device that is positioned in front of each corresponding memory device.

### Claim 3

A method of generating a PN code, the method comprising:
receiving a clock signal;
extracting at least two bit values from bit values that are output from a plurality of memory devices in correspondence to the clock signal;
outputting an XOR operation value with respect to the extracted at least two bit values; and
generating the PN code based on the output XOR operation value,
wherein:
the plurality of memory devices is cascaded, and
the method further comprises:
outputting an AND operation value with respect to a stored initial value of each of the memory devices and an output value of a memory device that is positioned in a final end among the plurality of cascaded memory devices, and
a memory device that is positioned in a front end among the plurality of cascaded memory devices receives an AND operation value with respect to an initial value of the memory device of the front end, and
each of memory devices excluding the memory device of the front end receives an XOR operation value with respect to an AND operation value associated with an initial value of each of the memory devices and an output value of the memory device that is disposed in front of each corresponding memory device.