# US 8,787,498 B2 · Systems and methods for enhanced carrier suppression > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,787,498 B2 - Document ID: US8787498B2 - Status: Granted - Kind: B2 - Application number: 13/212,691 - Filed: 2011-08-18 - Published: 2013-02-21 - Granted: 2014-07-22 - Earliest claimed: 2011-08-18 - Assignees: L-3 Communications Cincinnati Electronics Corporation - Applicants: Mark Dapore; Robert Hayes; Greg Rupp - Inventors: Mark Dapore; Robert Hayes; Greg Rupp - Web page: https://patentgrep.com/patent/US8787498B2 ## CPC - H04L 25/03343: {Arrangements at the transmitter end} - H04L 27/2071: {in which the data are represented by the carrier phase, e.g. systems with differential coding} - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract Included are embodiments for enhanced carrier suppression. One embodiment of a circuit includes a mixer that receives a cover sequence, the cover sequence including transition data from a first signal and a second signal. The mixer may be configured to generate a modulated cover sequence by modulating a radio frequency (RF) carrier with the cover sequence. Some embodiments also include a modulator that is communicatively coupled to the mixer. The modulator may be configured to receive and modulate an altered version of the first signal and an altered version of the second signal. The modulator may additionally receive the modulated cover sequence as an RF carrier input and generate an RF output by modulating the modulated cover sequence with the altered version of the first signal and the altered version of the second signal. ## Claims ### Claim 1 A system for enhanced carrier suppression, the system comprising: a digital logic block that receives a current version of a first signal, a delayed version of the first signal, a current version of a second signal and a delayed version of the second signal, the digital logic block configured to generate a cover sequence that includes only a subset of transitions from the current version of the first signal and the current version of the second signal, wherein the subset of transitions is less than all transitions from the current version of the first signal and the current version of the second signal, the digital logic block further configured to generate an altered version of the first signal and an altered version of the second signal that reflect transitions that remain after the subset of transitions have been removed; a mixer that is communicatively coupled to the digital logic block, the mixer configured to receive the cover sequence and configured to generate a modulated cover sequence by modulating a radio frequency (RF) carrier with the cover sequence, wherein the mixer includes a binary phase shift keyed (BPSK) modulator; a modulator that is communicatively coupled to the digital logic block, the modulator configured to receive the altered version of the first signal and the altered version of the second signal, the modulator configured to receive the modulated cover sequence as an RF carrier input, the modulator further configured to generate an RF output by modulating the modulated cover sequence with the altered version first the first signal and the altered version of the second signal; and a delay component coupled to the digital logic block and the modulator, the delay component configured to provide path equalization delays to the altered version of the first signal and the altered version of the second signal, wherein the system exhibits 40 dB of carrier suppression. ### Claim 2 (depends on 1) The system of claim 1, wherein the first signal is an in-phase data signal and the second signal is a quadrature data signal. ### Claim 3 (depends on 1) The system of claim 1, wherein the modulator includes a quadrature phase shift keying (QPSK) modulator. ### Claim 4 A circuit for enhanced carrier suppression, the circuit comprising: a digital logic block that receives a current version of a first signal, a delayed version of the first signal, a current version of a second signal and a delayed version of the second signal, the digital logic block configured to generate a cover sequence that includes only a subset of transitions from the current version of the first signal and the current version of the second signal, wherein the subset of transitions is less than all transitions from the current version of the first signal and the current version of the second signal, the digital logic block further configured to generate an altered version of the first signal and an altered version of the second signal that reflect transitions that remain after the subset of transitions have been removed; a mixer that is communicatively coupled to the digital logic block, the mixer configured to receive the cover sequence and configured to generate a modulated cover sequence by modulating a radio frequency (RF) carrier with the cover sequence, wherein the mixer includes a binary phase shift keyed (BPSK) modulator; a modulator that is communicatively coupled to the digital logic block, the modulator configured to receive the altered version of the first signal and the altered version of the second signal, the modulator configured to receive the modulated cover sequence as an RF carrier input, the modulator further configured to generate an RF output by modulating the modulated cover sequence with the altered version first the first signal and the altered version of the second signal; and a delay component coupled to the digital logic block and the modulator, the delay component configured to provide path equalization delays to the altered version of the first signal and the altered version of the second signal, wherein the circuit exhibits 40 dB of carrier suppression. ### Claim 5 (depends on 4) The circuit of claim 4, wherein the first signal is an in-phase data signal and the second signal is a quadrature data signal. ### Claim 6 (depends on 4) The circuit of claim 4, wherein the modulator includes a quadrature phase shift keying (QPSK) modulator. ### Claim 7 A method for enhanced carrier suppression, the method comprising: receiving a current version of a first signal, a delayed version of the first signal, a current version of a second signal and a delayed version of the second signal; generating a cover sequence that includes only a subset of transitions from the current version of the first signal and the current version of the second signal, wherein the subset of transitions is less than all transitions from the current version of the first signal and the current version of the second signal; generating an altered version of the first signal and an altered version of the second signal that reflect transitions that remain after the subset of transitions have been removed; receiving, by a binary phase shift keyed (BPSK) modulator, the cover sequence and generating a modulated cover sequence by modulating a radio frequency (RF) carrier with the cover sequence; receiving the altered version of the first signal and the altered version of the second signal; receiving the modulated cover sequence as an RF carrier input; generating an RF output by modulating the modulated cover sequence with the altered version first the first signal and the altered version of the second signal; and providing path equalization delays to the altered version of the first signal and the altered version of the second signal, wherein the method exhibits 40 dB of carrier suppression. ### Claim 8 (depends on 7) The method of claim 7, wherein the first and second signals are in-phase data signal and a quadrature data signal respectively. ### Claim 9 (depends on 7) The method of claim 7, wherein modulating the altered version of the plurality of signals includes utilizing a quadrature phase shift keying (QPSK) modulator. ### Claim 10 (depends on 7) The method of claim 7, further comprising sending the RF output signal to an antenna.