# US 8,787,471 B1 · Alignment of DigRF4 lane > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,787,471 B1 - Document ID: US8787471B1 - Status: Granted - Kind: B1 - Application number: 13/371,438 - Filed: 2012-02-12 - Granted: 2014-07-22 - Earliest claimed: 2011-02-15 - Assignees: Marvell International Ltd. - Applicants: Elad Lifshitz - Inventors: Elad Lifshitz - Web page: https://patentgrep.com/patent/US8787471B1 ## CPC - H04B 1/40: Circuits - H04B: TRANSMISSION ## Abstract A method includes receiving, over multiple serial interfaces arranged in parallel to couple between a transmitter and a receiver, a data burst which includes start-of-frame markers and is transmitted over the serial interfaces as multiple respective partial bursts such that each start-of-frame marker is transmitted over the multiple serial interfaces. A relative symbol offset between two or more start-of-frame markers on respective two or more of the serial interfaces is detected at the receiver. The data burst is decoded based on the detected relative symbol offset. ## Claims ### Claim 1 A method, comprising: receiving, over multiple serial interfaces arranged in parallel to couple between a transmitter and a receiver, a data burst which comprises start-of-frame markers and is transmitted over the serial interfaces as multiple respective partial bursts such that each start-of-frame marker is transmitted over the multiple serial interfaces; detecting at the receiver a relative symbol offset between two or more start-of-frame markers on respective two or more of the serial interfaces; and upon detecting a failure to receive a portion of the data burst, decoding the data burst by identifying, based on the detected relative symbol offset, a serial interface that carries a header of a data frame transmitted in the data burst, and re-establishing reception of the data burst subsequently to the portion by decoding the header on the determined serial interface. ### Claim 2 (depends on 1) The method according to claim 1, wherein detecting the relative symbol offset comprises correcting a synchronization error between the serial interfaces. ### Claim 3 A method, comprising: receiving, over multiple serial interfaces arranged in parallel to couple between a transmitter and a receiver, a data burst which comprises start-of-frame markers and is transmitted over the serial interfaces as multiple respective partial bursts such that each start-of-frame marker is transmitted over the multiple serial interfaces; detecting at the receiver a relative symbol offset between two or more start-of-frame markers on respective two or more of the serial interfaces; decoding the data burst by identifying, based on the detected relative symbol offset, a serial interface that carries a header of a data frame transmitted in the data burst; and defining one of the serial interfaces as a primary interface and another of the serial interfaces as a secondary interface, wherein identifying the serial interface that carries the header comprises: when the relative symbol offset between the start-of-frame markers in the primary interface and the secondary interface is zero, detecting that the primary interface carries the header; when a start-of-frame marker in the primary interface appears ahead of the start-of-frame marker in the secondary interface, detecting that the secondary interface carries the header; and when the start-of-frame marker in the secondary interface appears ahead of the start-of-frame marker in the primary interface, detecting that the primary interface carries the header. ### Claim 4 (depends on 1) The method according to claim 1, wherein receiving the partial bursts comprises accepting the partial bursts over respective lanes of a DigRF interface. ### Claim 5 (depends on 1) The method according to claim 1, wherein each of the partial bursts comprises a respective sequence of symbols each divided into Unit Intervals (UIs), and wherein decoding the data burst comprises reconstructing the data burst subject to accepting the partial bursts with a mutual timing offset that does not exceed four UIs. ### Claim 6 (depends on 1) The method according to claim 1, wherein detecting the relative symbol offset between the start-of-frame markers comprises correcting the relative symbol offset in the received partial bursts so as to match the relative symbol offset that is set when the data burst is transmitted over the serial interfaces. ### Claim 7 (depends on 6) The method according to claim 6, wherein correcting the relative symbol offset comprises compensating for a time delay between the serial interfaces. ### Claim 8 (depends on 6) The method according to claim 6, wherein correcting the relative symbol offset comprises compensating for timing skew between respective clock signals that clock the serial interfaces. ### Claim 9 (depends on 6) The method according claim 6, wherein correcting the relative symbol offset comprises applying a symbol delay to one of the received partial bursts. ### Claim 10 Apparatus, comprising: an input circuit, which is configured to receive, over multiple serial interfaces arranged in parallel, a data burst which comprises start-of-frame markers and is transmitted over the serial interfaces as multiple respective partial bursts such that each start-of-frame marker is transmitted over the multiple serial interfaces; and an alignment circuit, which is configured to detect a relative symbol offset between two or more start-of-frame markers on respective two or more of the serial interfaces, and, upon detecting a failure to receive a portion of the data burst, to decode the data burst by identifying, based on the detected relative symbol offset, a serial interface that carries a header of a data frame transmitted in the data burst, and re-establishing reception of the data burst subsequently to the portion by decoding the header on the determined serial interface. ### Claim 11 (depends on 10) The apparatus according to claim 10, wherein the alignment circuit is configured to correct a synchronization error between the serial interfaces. ### Claim 12 Apparatus, comprising: an input circuit, which is configured to receive, over multiple serial interfaces arranged in parallel, a data burst which comprises start-of-frame markers and is transmitted over the serial interfaces as multiple respective partial bursts such that each start-of-frame marker is transmitted over the multiple serial interfaces; and an alignment circuit, which is configured to detect a relative symbol offset between two or more start-of-frame markers on respective two or more of the serial interfaces, to decode the data burst based on the detected relative symbol offset, to define one of the serial interfaces as a primary interface and another of the serial interfaces as a secondary interface, and to identify the serial interface that carries the header by: when the relative symbol offset between the start-of-frame markers in the primary interface and the secondary interface is zero, detecting that the primary interface carries the header; when a start-of-frame marker in the primary interface appears ahead of the start-of-frame marker in the secondary interface, detecting that the secondary interface carries the header; and when the start-of-frame marker in the secondary interface appears ahead of the start-of-frame marker in the primary interface, detecting that the primary interface carries the header. ### Claim 13 (depends on 10) The apparatus according to claim 10, wherein the alignment circuit is configured to correct the relative symbol offset in the received partial bursts so as to match the relative symbol offset that is set when the data burst is transmitted over the serial interfaces. ### Claim 14 (depends on 13) The apparatus according to claim 13, wherein the alignment circuit is configured to correct the relative symbol offset by performing at least one action selected from among: compensating for a time delay between the serial interfaces; compensating for timing skew between respective clock signals that clock the serial interfaces; and applying a symbol delay to one of the received partial bursts. ### Claim 15 (depends on 10) A mobile communication terminal comprising the apparatus of claim 10. ### Claim 16 (depends on 10) A chipset for processing signals in a mobile communication terminal, comprising the apparatus of claim 10.