# US 8,787,464 B1 · Hadamard transformation of data for video compression

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- Number: US 8,787,464 B1
- Document ID: US8787464B1
- Status: Granted
- Kind: B1
- Application number: 11/657,927
- Filed: 2007-01-24
- Granted: 2014-07-22
- Earliest claimed: 2006-02-10
- Assignees: NVIDIA Corporation
- Applicants: Pankaj Chaurasia; Shankar Moni
- Inventors: Pankaj Chaurasia; Shankar Moni
- Web page: https://patentgrep.com/patent/US8787464B1

## CPC

- H04N 19/423: characterised by memory arrangements (H04N19/433 takes precedence)
- H04N 19/61: in combination with predictive coding
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION

## Abstract

A video processor is described, which is useful for implementing a Hadamard transform process, in compliance with the H.264 standard. The video processor includes an input, for receiving a block of image data. The image data is loaded into an internal register. In response to receiving a SIMD instruction, a multiplier, which incorporates the H.264 Hadamard transform matrix in its associated hardware, processes the block of image data, and writes the resulting partially transformed pixel data back to the internal register, transposing the data during the process.

## Claims

### Claim 1

A video processor comprising:
an input for receiving a Direct-Current (DC) block, said DC block comprising a plurality of DC values;
an internal register for storing said plurality of DC values;
a multiplier, comprising a Hadamard transform matrix and configured to receive Single Instruction Multiple Data (SIMD) instructions, wherein upon receiving a first transform SIMD instruction, said multiplier operable to perform a 1-D Hadamard transform of said plurality of DC values using said Hadamard transform matrix, operable to produce a partially transformed plurality of DC values, and further operable to write said partially transformed plurality of DC values directly in a transposed manner to said internal register as transposed plurality of DC values to save processor cycles; and
wherein upon receiving a second transform SIMD instruction, said multiplier is operable to perform a 1-D Hadamard transform of said transposed plurality of DC values using said Hadamard transform matrix, producing a Hadamard transformed plurality of DC values, and is operable to write said Hadamard transformed plurality of DC values directly in a transposed manner to said internal register to save processor cycles.

### Claim 2 (depends on 1)

The video processor of claim 1, wherein said internal register comprises a 16 element SIMD vector.

### Claim 3 (depends on 2)

The video processor of claim 2, wherein said internal register comprises a 256 bit register.

### Claim 4 (depends on 1)

The video processor of claim 1, wherein said multiplier comprises a plurality of bit shifters, a plurality of adders, and a plurality of sign changing gates.

### Claim 5 (depends on 4)

The video processor of claim 4, wherein said transform matrix is implemented as a first subset of said plurality of bit shifters, a second subset of said plurality of adders, and a third subset of said plurality of sign changing gates.

### Claim 6 (depends on 1)

The video processor of claim 1, wherein said video processor resides within a central processing unit (CPU).

### Claim 7 (depends on 1)

The video processor of claim 1, wherein said video processor resides within an expansion card configured for use with a computing system.

### Claim 8

A method comprising:
loading a plurality of pixel data corresponding to a block of image data into a single register;
in response to receiving a first Hadamard transform Single Instruction Multiple Data (SIMD) instruction from a software controller, processing said plurality of pixel data in a hardware processor, said processing comprising multiplying said plurality of pixel data by a hardware-implemented Hadamard transform matrix to produce a plurality of transformed pixel data and writing said plurality of transformed pixel data directly in a transposed form into said single register as a plurality of transposed intermediary data to save processor cycles; and
in response to receiving a second Hadamard transform Single Instruction Multiple Data (SIMD) instruction from a software controller, further processing said plurality of transposed intermediary data in said hardware processor by multiplying said plurality of transposed intermediary data by said Hadamard transform matrix to produce a result and writing the result directly in a transposed form into said single register as a plurality of Hadamard transformed data to save processor cycles.

### Claim 9 (depends on 8)

The method of claim 8, further comprising writing said plurality of Hadamard transformed data to a memory of a computer system.

### Claim 10 (depends on 8)

The method of claim 8, wherein said single register comprises a SI MD vector of 16 elements.

### Claim 11 (depends on 8)

The method of claim 8, wherein said Hadamard transform operation is related to a version of the H.264 video compression standard.

### Claim 12 (depends on 8)

The method of claim 8, wherein said hardware-implemented Hadamard transform matrix comprises a plurality of adders, bit shifters and sign-changing hardware connected by paths.

### Claim 13

A computing system comprising:
a bus;
a processor coupled to said bus;
a memory coupled to said bus; and
a video processor coupled to said bus, said video processor comprising:
an input for receiving a block of image data, said image data comprising a plurality of pixel data;
an internal register for storing said plurality of pixel data;
a multiplier, comprising a transform matrix and configured to receive Single Instruction Multiple Data (SIMD) instructions from a software control structure, wherein upon receiving a Hadamard transform SIMD instruction, said multiplier is operable to perform a 1-D transform of said plurality of pixel data utilizing said transform matrix, producing a partially transformed plurality of pixel data, is operable to write said partially transformed plurality of pixel data directly in a transposed manner to said internal register as transposed plurality of pixel data to save processor cycles, is operable to perform a 1-D transform of said transposed plurality of pixel data utilizing said transform matrix, producing a Hadamard transformed plurality of pixel data and is operable to write said Hadamard transformed plurality of pixel data directly in a transposed manner to said internal register to save processor cycles.

### Claim 14 (depends on 13)

The computing system of claim 13, wherein said transform matrix comprises a Hadamard transform matrix associated with the H.264 video compression standard.

### Claim 15 (depends on 14)

The computing system of claim 14, further comprising:
a camera assembly, coupled to said bus; and
a digital data storage, coupled to said bus, wherein said camera assembly and digital data storage are configured to record digital video data.

### Claim 16 (depends on 15)

The computing system of claim 15, wherein said computing system resides within a mobile telephone.

### Claim 17 (depends on 15)

The computing system of claim 15, wherein said computing system resides within a digital camcorder.

### Claim 18 (depends on 15)

The computing system of claim 15, wherein said computing system resides within a webcam.

### Claim 19 (depends on 1)

The video processor of claim 1, wherein said partially transformed plurality of DC values are transposed via writing said partially transformed plurality of DC values into said internal register.

### Claim 20 (depends on 1)

The video processor of claim 1, wherein said first transform SIMD instruction is operable for a forward Hadamard transform and an inverse Hadamard transform.