# US 8,787,110 B2 · Realignment of command slots after clock stop exit

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- Number: US 8,787,110 B2
- Document ID: US8787110B2
- Status: Granted
- Kind: B2
- Application number: 13/537,688
- Filed: 2012-06-29
- Published: 2014-01-02
- Granted: 2014-07-22
- Earliest claimed: 2012-06-29
- Assignees: Intel Corporation
- Applicants: Tuan M. Quach; Victor V. Tran
- Inventors: Tuan M. Quach; Victor V. Tran
- Web page: https://patentgrep.com/patent/US8787110B2

## CPC

- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- G11C 5/066: {Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals}
- G11C 7/1057: {Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load}
- G11C 7/1063: {Control signal output circuits, e.g. status or busy flags, feedback command signals}
- G11C 7/1084: {Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load}
- G11C 7/1096: {Write circuits, e.g. I/O line write drivers}
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G11C 7/1069: {I/O lines read out arrangements}
- G11C 7/109: {Control signal input circuits}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Described herein are embodiments of dynamic command slot realignment after clock stop exit. An apparatus configured for dynamic command slot realignment after clock stop exit may include memory including a first memory module configured to receive commands over a first channel via a first command slot and a second memory module configured to receive commands over a second channel via a second command slot, and a memory buffer configured to receive a clock sync command targeting the first command slot, and perform a write pointer exchange in response to detecting the clock sync command in the second command slot to realign the first command slot and the second command slot. Other embodiments may be described and/or claimed.

## Claims

### Claim 1

An apparatus comprising:
a memory buffer configured to interface with a first memory module over a first channel via a first command slot and with a second memory module over a second channel via a second command slot, receive a clock sync command targeting the first command slot, and perform a write pointer exchange in response to detecting the clock sync command in the second command slot to realign the first command slot and the second command slot.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the memory buffer is configured to decode the clock sync command and perform the write pointer exchange after exiting a clock stop mode.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein during the clock stop mode, a memory command clock of the apparatus is stopped.

### Claim 4 (depends on 1)

The apparatus of claim 1, further comprising memory including the first memory module and the second memory module.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the memory comprises a double data rate (DDR) memory.

### Claim 6 (depends on 5)

The apparatus of claim 5, wherein the DDR memory comprises DDR dynamic random access memory.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the memory buffer includes a clock sync decoder coupled to a first command bus and a second command bus, and a slot detector coupled to the clock sync decoder for detecting whether the clock sync command is in the first command slot or the second command slot.

### Claim 8 (depends on 7)

The apparatus of claim 7, wherein the slot detector is configured to output a swap signal to a write enable controller for performing the write pointer exchange.

### Claim 9

A system comprising:
a host configured to issue a plurality of memory access commands;
memory including a first memory module configured to receive first memory access commands over a first channel via a first command slot and a second memory module configured to receive second memory access commands over a second channel via a second command slot;
a memory buffer configured to receive a clock sync command from the host targeting the first command slot, and perform a write pointer exchange in response to detecting the clock sync command in the second command slot to realign the first command slot and the second command slot; and
a display device operatively coupled to the host.

### Claim 10 (depends on 9)

The system of claim 9, wherein the host is configured to drive a core clock and a memory command clock.

### Claim 11 (depends on 10)

The system of claim 10, wherein the host is configured to selectively disable the memory command clock in a clock stop mode.

### Claim 12 (depends on 11)

The system of claim 11, wherein the memory buffer is configured to decode the clock sync command and perform the write pointer exchange after exiting the clock stop mode.

### Claim 13 (depends on 9)

The system of claim 9, further comprising a network interface operatively coupled with the host, and configured to communicatively couple the system with a network.

### Claim 14 (depends on 9)

The system of claim 9, wherein the system is a selected one of a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant, an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video reorder.

### Claim 15 (depends on 9)

The system of claim 9, wherein the display device is a touch screen display.

### Claim 16 (depends on 9)

The system of claim 9, wherein the host includes one or more processors.

### Claim 17

A method comprising:
resuming a memory command clock;
receiving a clock sync command targeting a first command slot; and
performing a write pointer exchange in response to detecting the clock sync command in a second command slot to realign the first command slot and the second command slot.

### Claim 18 (depends on 17)

The method of claim 17, wherein the performing the write pointer exchange comprising performing the write point exchange after exiting a clock stop mode.

### Claim 19 (depends on 17)

The method of claim 17, further comprising selectively disabling the memory command clock in a clock stop mode.

### Claim 20 (depends on 17)

The method of claim 17, further comprising decoding the clock sync command prior to performing the write pointer exchange.

### Claim 21 (depends on 17)

The method of claim 17, wherein the performing the write pointer exchange comprises outputting a swap signal by a command slot swap controller to a write enable controller.

### Claim 22

A non-transitory machine-readable medium having associated instructions that, when executed by a machine, result in operations including:
resuming a memory command clock;
receiving a clock sync command targeting a first command slot; and
performing a write pointer exchange in response to detecting the clock sync command in a second command slot to realign the first command slot and the second command slot.

### Claim 23 (depends on 22)

The non-transitory machine-readable medium of claim 22, wherein the performing the write pointer exchange is performed after exiting a clock stop mode.

### Claim 24 (depends on 22)

The non-transitory machine-readable medium of claim 22, wherein the operations further include selectively disabling the memory command clock in a clock stop mode.

### Claim 25 (depends on 22)

The non-transitory machine-readable medium of claim 22, wherein the operations further include decoding the clock sync command prior to performing the write pointer exchange.