# US 8,787,107 B2 · Memory device power control

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- Number: US 8,787,107 B2
- Document ID: US8787107B2
- Status: Granted
- Kind: B2
- Application number: 14/174,570
- Filed: 2014-02-06
- Published: 2014-06-05
- Granted: 2014-07-22
- Earliest claimed: 2012-03-16
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Marco Sforzin
- Web page: https://patentgrep.com/patent/US8787107B2

## CPC

- G11C 5/14: Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels}
- G11C 5/141: {Battery and back-up supplies}
- G11C 5/143: {Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels (G11C5/148 takes precedence); Switching between alternative supplies (G11C5/141 takes precedence)}
- G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
- G11C 16/30: Power supply circuits
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

The apparatus described herein may comprise a first set of transistors, including a first transistor and a second transistor, and a second set of transistors, including a third transistor and a fourth transistor. Gates of the first and second transistors may be coupled to a first signal and a second signal, respectively, each indicating whether a corresponding one of a first supply voltage and a second supply voltage reaches a first threshold voltage or a second threshold voltage to power on a first circuit or a second circuit of a memory device. Gates of the third and fourth transistors may be coupled to a first inverted version of the first signal and a second inverted version of the second signal, respectively. An outcome signal of the second set of transistors may indicate a power-on state of the memory device responsive to power states of the first and second signals.

## Claims

### Claim 1

An apparatus comprising:
a first set of transistors including a first transistor and a second transistor, gates of the first and second transistors to couple to a first supply voltage, and a source or a drain of the first transistor coupled to at least one diode to couple to a second supply voltage, the first supply voltage to power on a first circuit of a memory device and having a first voltage range and the second supply voltage to power on a second circuit of the memory device and having a second voltage range different from the first voltage range;
a second set of transistors including a third transistor and a fourth transistor, gates of the third and fourth transistors coupled to one or more of the first set of transistors, a source or a drain of the third transistor coupled to at least one leaker to couple to the second supply voltage, and a source or a drain of the fourth transistor to couple to an outcome signal, the outcome signal to be generated responsive to a voltage within the second voltage range and indicating whether the first supply voltage reaches a threshold voltage to power on the first circuit; and
one or more transistors including a fifth transistor, a gate of the fifth transistor coupled to the at least one leaker and the source or the drain of the third transistor.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the first transistor comprises a first one of a PMOS transistor and an NMOS transistor, and the second transistor comprises a second one of the PMOS transistor and the NMOS transistor.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the third transistor comprises a first one of a PMOS transistor and an NMOS transistor, and the fourth transistor comprises a second one of the PMOS transistor and the NMOS transistor.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein the fifth transistor comprises a same type of transistor as the first and third transistors.

### Claim 5 (depends on 3)

The apparatus of claim 3, wherein a source or a drain of the fifth transistor is to couple to the second supply voltage.

### Claim 6 (depends on 3)

The apparatus of claim 3, further comprising:
a pull-down leaker coupled to a source or a drain of the fifth transistor and configured to resolve a floating state of the outcome signal.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the third transistor is coupled in parallel with the fourth transistor.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein the apparatus is configured to start a power-on operational sequence of the device only after the first and second supply voltages have reached a corresponding one of the first and second threshold voltages.

### Claim 9 (depends on 1)

The apparatus of claim 1, wherein the at least one or more transistor is included in a pull-up path configured to boost the outcome signal based on a level of the second supply voltage.

### Claim 10 (depends on 1)

The apparatus of claim 1, wherein the apparatus is configured to provide an indication associated with the second supply voltage before providing an indication associated with the first supply voltage.

### Claim 11 (depends on 10)

The apparatus of claim 10, wherein a first one of a source and a drain of the fifth transistor is to couple to the second supply voltage, and a second one of the source and the drain of the fifth transistor is to couple to the outcome signal.

### Claim 12 (depends on 11)

The apparatus of claim 11, further comprising:
an additional diode coupled to a source or a drain of the second transistor that is not coupled to the first transistor, the additional diode configured to increase the threshold voltage to power on the first circuit.

### Claim 13 (depends on 1)

The apparatus of claim 1, further comprising:
a first voltage detector to couple to the first supply voltage to generate a first outcome signal indicating whether the first supply voltage reaches a threshold voltage to power on the first circuit of the memory device.

### Claim 14 (depends on 13)

The apparatus of claim 13, further comprising:
a second voltage detector to couple to the second supply voltage to generate a second outcome signal indicating whether the second supply voltage has reached a threshold voltage to power on the second circuit of the memory device.

### Claim 15 (depends on 14)

The apparatus of claim 14, further comprising:
a core swing logic configured to generate a third outcome signal based on the first and second outcome signals, the third outcome signal indicating a power-on state of the memory device.

### Claim 16 (depends on 15)

The apparatus of claim 15, wherein the core swing logic comprises at least one logic gate coupled to the first voltage detector and configured to reduce a level of the first outcome signal to provide a low voltage signal.

### Claim 17 (depends on 16)

The apparatus of claim 16, wherein the core swing logic comprises a first additional transistor having a gate to couple to the low voltage signal.

### Claim 18 (depends on 17)

The apparatus of claim 17, wherein the core swing logic comprises an edge detector coupled to the second voltage detector and configured to detect a rising edge of the second outcome signal for a specified period of time.

### Claim 19 (depends on 18)

The apparatus of claim 18, wherein the core swing logic comprises a second additional having a gate coupled to the edge detector, and the strength of the additional transistor being less than that of the first additional transistor.

### Claim 20 (depends on 19)

The apparatus of claim of claim 19, wherein the core swing logic comprises a set of logic gates including a first logic gate, a second logic gate and a third logic gate, the first logic gate coupled to a source or a drain of the first additional transistor and a source or a drain of the second additional transistor, the second logic gate coupled to the source or the drain of the first additional transistor and the source or the drain of the second additional transistor, the third logic gate coupled to the first logic gate, the second logic gate, and the second additional transistor, and the third logic gate to couple to the third outcome signal.