# US 8,787,105 B2 · Dynamic random access memory with multiple thermal sensors disposed therein and control method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,787,105 B2 - Document ID: US8787105B2 - Status: Granted - Kind: B2 - Application number: 13/468,987 - Filed: 2012-05-10 - Published: 2013-11-14 - Granted: 2014-07-22 - Earliest claimed: 2012-05-10 - Assignees: Nanya Technology Corporation - Applicants: Chih-Jen Chen - Inventors: Chih-Jen Chen - Web page: https://patentgrep.com/patent/US8787105B2 ## CPC - G11C 11/40615: {Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs} - G11C 11/40626: {Temperature related aspects of refresh operations} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A dynamic random access memory (DRAM) with multiple thermal sensors disposed therein and a control method for the DRAM. A DRAM in accordance with an exemplary embodiment of the invention provides multi-zone temperature detection. The DRAM comprises a plurality of banks, a plurality of thermal sensors and a control unit. The thermal sensors are disposed between the banks. The control unit controls the thermal sensors to obtain sensed temperatures, and sets a self-refresh cycle for all of the banks based on the highest one of the sensed temperatures. ## Claims ### Claim 1 A dynamic random access memory with multi-zone temperature detection, comprising: a plurality of banks; a plurality of thermal sensors disposed between the plurality of banks; and a control unit, controlling the plurality of thermal sensors to obtain sensed temperatures, and setting a self-refresh cycle for all of the banks based on the highest one of the sensed temperatures. ### Claim 2 (depends on 1) The dynamic random access memory as claimed in claim 1, wherein the control unit further sets partial array self-refresh cycles for unmasked banks of the plurality of banks separately and, for each unmasked bank, the partial array self-refresh cycle corresponding thereto is set according to the thermal condition thereof. ### Claim 3 (depends on 2) The dynamic random access memory as claimed in claim 2, wherein the control unit further selects the unmasked bank at the lowest temperature compared to the other unmasked banks to store critical data. ### Claim 4 (depends on 1) The dynamic random access memory as claimed in claim 1, wherein the control unit comprises a thermal sensor control circuit which comprises: a decoder, decoding a thermal sensor address and thereby outputting decoded bits; a plurality of AND gates, wherein each of the plurality of AND gates comprises a first input terminal, a second input terminal and an output terminal, and the first input terminals of the AND gates are all controlled by a thermal detection enable signal while the second input terminals of the AND gates are controlled by the decoded bits, respectively, and the output terminals of the AND gates are coupled to the plurality of thermal sensors, respectively, to enable the thermal sensor indicated by the thermal sensor address. ### Claim 5 (depends on 4) The dynamic random access memory as claimed in claim 4, wherein the thermal sensor control circuit further comprises: a status register read register coupled to the plurality of the thermal sensors to receive the sensed temperature of the enabled thermal sensor; and data in/out lines coupled to the status register read register, wherein the thermal sensors which are not enabled have relatively high impedance to the enabled thermal sensor. ### Claim 6 (depends on 5) The dynamic random access memory as claimed in claim 5, wherein the control unit further comprises a mode register through which the thermal sensor address is provided to the decoder. ### Claim 7 (depends on 6) The dynamic random access memory as claimed in claim 6, wherein the control unit is further coupled to a DRAM controller which retrieves the status register read register via the data in/out lines to collect the sensed temperatures of the plurality of the thermal sensors. ### Claim 8 (depends on 7) The dynamic random access memory as claimed in claim 7, wherein the thermal sensor control circuit further comprises a temperature-compensated self-refresh circuit coupled to the plurality of thermal sensors and, to operate the dynamic random access memory in a self-refresh mode, the DRAM controller compares the collected sensed temperatures to obtain the thermal sensor at the highest temperature and reassigns the thermal sensor address through the mode register to indicate the thermal sensor at the highest temperature and thereby operates the decoder again. ### Claim 9 (depends on 8) The dynamic random access memory as claimed in claim 8, wherein when the dynamic random access memory is in the self-refresh mode the temperature-compensated self-refresh circuit receives the sensed temperature of the thermal sensor indicated by the reassigned thermal sensor address and calculates the self-refresh cycle based on the received sensed temperature and self-refreshes all of the plurality of the banks according the self-refresh cycle. ### Claim 10 (depends on 6) The dynamic random access memory as claimed in claim 6, wherein the mode register is further coupled to a DRAM controller which provides the decoder with the thermal sensor address via the mode register. ### Claim 11 (depends on 10) The dynamic random access memory as claimed in claim 10, wherein the thermal sensor control circuit further comprises a temperature-compensated self-refresh circuit coupled to the plurality of thermal sensors and, to operate the dynamic random access memory in a partial array self-refresh mode, the thermal sensor address provided by the DRAM controller indicates the thermal sensor corresponding to a selected unmasked bank selected from the unmasked banks. ### Claim 12 (depends on 11) The dynamic random access memory as claimed in claim 11, wherein when the dynamic random access memory is in the partial array self-refresh mode, the temperature-compensated self-refresh circuit receives the sensed temperature of the selected unmasked bank and calculates the partial array self-refresh cycle of the selected unmasked bank based on the received sensed temperature and performs a partial array self-refresh operation on the selected unmasked bank according to the partial array self-refresh cycle. ### Claim 13 A method for controlling a dynamic random access memory having a plurality of thermal sensors disposed between banks of the dynamic random access memory, comprising: controlling the plurality of thermal sensors to obtain sensed temperatures, and setting a self-refresh cycle for all of the banks based on the highest one of the sensed temperatures. ### Claim 14 (depends on 13) The method as claimed in claim 13, further comprising: setting partial array self-refresh cycles for unmasked banks of the plurality of banks separately, wherein for each unmasked bank the partial array self-refresh cycle corresponding thereto is set according to the thermal condition thereof. ### Claim 15 (depends on 14) The method as claimed in claim 14, further comprising: using the unmasked bank at the lowest temperature compared to the other unmasked banks to store critical data.